2 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
4 * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC))
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 typedef struct at91_emac {
74 #define AT91_EMAC_CTL_LB 0x0001
75 #define AT91_EMAC_CTL_LBL 0x0002
76 #define AT91_EMAC_CTL_RE 0x0004
77 #define AT91_EMAC_CTL_TE 0x0008
78 #define AT91_EMAC_CTL_MPE 0x0010
79 #define AT91_EMAC_CTL_CSR 0x0020
80 #define AT91_EMAC_CTL_ISR 0x0040
81 #define AT91_EMAC_CTL_WES 0x0080
82 #define AT91_EMAC_CTL_BP 0x1000
84 #define AT91_EMAC_CFG_SPD 0x0001
85 #define AT91_EMAC_CFG_FD 0x0002
86 #define AT91_EMAC_CFG_BR 0x0004
87 #define AT91_EMAC_CFG_CAF 0x0010
88 #define AT91_EMAC_CFG_NBC 0x0020
89 #define AT91_EMAC_CFG_MTI 0x0040
90 #define AT91_EMAC_CFG_UNI 0x0080
91 #define AT91_EMAC_CFG_BIG 0x0100
92 #define AT91_EMAC_CFG_EAE 0x0200
93 #define AT91_EMAC_CFG_CLK_MASK 0xFFFFF3FF
94 #define AT91_EMAC_CFG_MCLK_8 0x0000
95 #define AT91_EMAC_CFG_MCLK_16 0x0400
96 #define AT91_EMAC_CFG_MCLK_32 0x0800
97 #define AT91_EMAC_CFG_MCLK_64 0x0C00
98 #define AT91_EMAC_CFG_RTY 0x1000
99 #define AT91_EMAC_CFG_RMII 0x2000
101 #define AT91_EMAC_SR_LINK 0x0001
102 #define AT91_EMAC_SR_MDIO 0x0002
103 #define AT91_EMAC_SR_IDLE 0x0004
105 #define AT91_EMAC_TCR_LEN(x) (x & 0x7FF)
106 #define AT91_EMAC_TCR_NCRC 0x8000
108 #define AT91_EMAC_TSR_OVR 0x0001
109 #define AT91_EMAC_TSR_COL 0x0002
110 #define AT91_EMAC_TSR_RLE 0x0004
111 #define AT91_EMAC_TSR_TXIDLE 0x0008
112 #define AT91_EMAC_TSR_BNQ 0x0010
113 #define AT91_EMAC_TSR_COMP 0x0020
114 #define AT91_EMAC_TSR_UND 0x0040
116 #define AT91_EMAC_RSR_BNA 0x0001
117 #define AT91_EMAC_RSR_REC 0x0002
118 #define AT91_EMAC_RSR_OVR 0x0004
120 /* ISR, IER, IDR, IMR use the same bits */
121 #define AT91_EMAC_IxR_DONE 0x0001
122 #define AT91_EMAC_IxR_RCOM 0x0002
123 #define AT91_EMAC_IxR_RBNA 0x0004
124 #define AT91_EMAC_IxR_TOVR 0x0008
125 #define AT91_EMAC_IxR_TUND 0x0010
126 #define AT91_EMAC_IxR_RTRY 0x0020
127 #define AT91_EMAC_IxR_TBRE 0x0040
128 #define AT91_EMAC_IxR_TCOM 0x0080
129 #define AT91_EMAC_IxR_TIDLE 0x0100
130 #define AT91_EMAC_IxR_LINK 0x0200
131 #define AT91_EMAC_IxR_ROVR 0x0400
132 #define AT91_EMAC_IxR_HRESP 0x0800
134 #define AT91_EMAC_MAN_DATA_MASK 0xFFFF
135 #define AT91_EMAC_MAN_CODE_802_3 0x00020000
136 #define AT91_EMAC_MAN_REGA(reg) ((reg & 0x1F) << 18)
137 #define AT91_EMAC_MAN_PHYA(phy) ((phy & 0x1F) << 23)
138 #define AT91_EMAC_MAN_RW_R 0x20000000
139 #define AT91_EMAC_MAN_RW_W 0x10000000
140 #define AT91_EMAC_MAN_HIGH 0x40000000
141 #define AT91_EMAC_MAN_LOW 0x80000000