1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2016 Google, Inc
5 #ifndef _ASM_ARCH_TIMER_H
6 #define _ASM_ARCH_TIMER_H
8 /* Each timer has 4 control bits in ctrl1 register.
9 * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on,
10 * such that timer X uses bits (4 * X - 4):(4 * X - 1)
11 * If the timer does not support PWM, bit 4 is reserved.
13 #define AST_TMC_EN (1 << 0)
14 #define AST_TMC_1MHZ (1 << 1)
15 #define AST_TMC_OVFINTR (1 << 2)
16 #define AST_TMC_PWM (1 << 3)
18 /* Timers are counted from 1 in the datasheet. */
19 #define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1))
21 #define AST_TMC_RATE (1000*1000)
26 * All timers share control registers, which makes it harder to make them
27 * separate devices. Since only one timer is needed at the moment, making
28 * it this just one device.
31 struct ast_timer_counter {
39 struct ast_timer_counter timers1[3];
42 #ifdef CONFIG_ASPEED_AST2500
48 struct ast_timer_counter timers2[5];
51 #endif /* __ASSEMBLY__ */
53 #endif /* _ASM_ARCH_TIMER_H */