2 * Copyright (c) 2016 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_SCU_AST2500_H
7 #define _ASM_ARCH_SCU_AST2500_H
9 #define SCU_UNLOCK_VALUE 0x1688a8a8
11 #define SCU_HWSTRAP_VGAMEM_MASK 3
12 #define SCU_HWSTRAP_VGAMEM_SHIFT 2
13 #define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
14 #define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
15 #define SCU_HWSTRAP_DDR4 (1 << 24)
16 #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23)
18 #define SCU_MPLL_DENUM_SHIFT 0
19 #define SCU_MPLL_DENUM_MASK 0x1f
20 #define SCU_MPLL_NUM_SHIFT 5
21 #define SCU_MPLL_NUM_MASK 0xff
22 #define SCU_MPLL_POST_SHIFT 13
23 #define SCU_MPLL_POST_MASK 0x3f
24 #define SCU_PCLK_DIV_SHIFT 23
25 #define SCU_PCLK_DIV_MASK 7
26 #define SCU_HPLL_DENUM_SHIFT 0
27 #define SCU_HPLL_DENUM_MASK 0x1f
28 #define SCU_HPLL_NUM_SHIFT 5
29 #define SCU_HPLL_NUM_MASK 0xff
30 #define SCU_HPLL_POST_SHIFT 13
31 #define SCU_HPLL_POST_MASK 0x3f
33 #define SCU_MISC2_UARTCLK_SHIFT 24
35 #define SCU_MISC_UARTCLK_DIV13 (1 << 12)
38 * SYSRESET is actually more like a Power register,
39 * except that corresponding bit set to 1 means that
40 * the peripheral is off.
42 #define SCU_SYSRESET_XDMA (1 << 25)
43 #define SCU_SYSRESET_MCTP (1 << 24)
44 #define SCU_SYSRESET_ADC (1 << 23)
45 #define SCU_SYSRESET_JTAG (1 << 22)
46 #define SCU_SYSRESET_MIC (1 << 18)
47 #define SCU_SYSRESET_SDIO (1 << 16)
48 #define SCU_SYSRESET_USB11HOST (1 << 15)
49 #define SCU_SYSRESET_USBHUB (1 << 14)
50 #define SCU_SYSRESET_CRT (1 << 13)
51 #define SCU_SYSRESET_MAC2 (1 << 12)
52 #define SCU_SYSRESET_MAC1 (1 << 11)
53 #define SCU_SYSRESET_PECI (1 << 10)
54 #define SCU_SYSRESET_PWM (1 << 9)
55 #define SCU_SYSRESET_PCI_VGA (1 << 8)
56 #define SCU_SYSRESET_2D (1 << 7)
57 #define SCU_SYSRESET_VIDEO (1 << 6)
58 #define SCU_SYSRESET_LPC (1 << 5)
59 #define SCU_SYSRESET_HAC (1 << 4)
60 #define SCU_SYSRESET_USBHID (1 << 3)
61 #define SCU_SYSRESET_I2C (1 << 2)
62 #define SCU_SYSRESET_AHB (1 << 1)
63 #define SCU_SYSRESET_SDRAM_WDT (1 << 0)
65 /* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
66 #define SCU_PINMUX_CTRL5_I2C (1 << 16)
69 * The values are grouped by function, not by register.
70 * They are actually scattered across multiple loosely related registers.
72 #define SCU_PIN_FUN_MAC1_MDC (1 << 30)
73 #define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
74 #define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
75 #define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
76 #define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
77 #define SCU_PIN_FUN_SCL1 (1 << 12)
78 #define SCU_PIN_FUN_SCL2 (1 << 14)
79 #define SCU_PIN_FUN_SDA1 (1 << 13)
80 #define SCU_PIN_FUN_SDA2 (1 << 15)
84 struct ast2500_clk_priv {
85 struct ast2500_scu *scu;
93 u32 freq_counter_ctrl;
103 u32 vga_handshake[2];
116 u32 mac_clk_delay_100M;
117 u32 mac_clk_delay_10M;
125 u32 freerun_counter_ext;
126 u32 clk_duty_meas_ctrl;
127 u32 clk_duty_meas_res;
129 /* The next registers are not key-protected */
130 struct ast2500_cpu2 {
136 u32 d_pll_ext_param[3];
137 u32 d2_pll_ext_param[3];
138 u32 mh_pll_ext_param;
146 u32 reloc_ctrl_decode[2];
148 u32 shared_sram_decode[2];
157 * ast_get_clk() - get a pointer to Clock Driver
159 * @devp, OUT - pointer to Clock Driver
160 * @return zero on success, error code (< 0) otherwise.
162 int ast_get_clk(struct udevice **devp);
165 * ast_get_scu() - get a pointer to SCU registers
167 * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise
169 void *ast_get_scu(void);
172 * ast_scu_unlock() - unlock protected registers
174 * @scu, pointer to ast2500_scu
176 void ast_scu_unlock(struct ast2500_scu *scu);
179 * ast_scu_lock() - lock protected registers
181 * @scu, pointer to ast2500_scu
183 void ast_scu_lock(struct ast2500_scu *scu);
185 #endif /* __ASSEMBLY__ */
187 #endif /* _ASM_ARCH_SCU_AST2500_H */