2 * Copyright (c) 2016 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_SCU_AST2500_H
7 #define _ASM_ARCH_SCU_AST2500_H
9 #define SCU_UNLOCK_VALUE 0x1688a8a8
11 #define SCU_HWSTRAP_VGAMEM_MASK 3
12 #define SCU_HWSTRAP_VGAMEM_SHIFT 2
13 #define SCU_HWSTRAP_DDR4 (1 << 24)
14 #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23)
16 #define SCU_MPLL_DENUM_SHIFT 0
17 #define SCU_MPLL_DENUM_MASK 0x1f
18 #define SCU_MPLL_NUM_SHIFT 5
19 #define SCU_MPLL_NUM_MASK 0xff
20 #define SCU_MPLL_POST_SHIFT 13
21 #define SCU_MPLL_POST_MASK 0x3f
23 #define SCU_HPLL_DENUM_SHIFT 0
24 #define SCU_HPLL_DENUM_MASK 0x1f
25 #define SCU_HPLL_NUM_SHIFT 5
26 #define SCU_HPLL_NUM_MASK 0xff
27 #define SCU_HPLL_POST_SHIFT 13
28 #define SCU_HPLL_POST_MASK 0x3f
30 #define SCU_MISC2_UARTCLK_SHIFT 24
32 #define SCU_MISC_UARTCLK_DIV13 (1 << 12)
36 struct ast2500_clk_priv {
37 struct ast2500_scu *scu;
45 u32 freq_counter_ctrl;
68 u32 mac_clk_delay_100M;
69 u32 mac_clk_delay_10M;
77 u32 freerun_counter_ext;
78 u32 clk_duty_meas_ctrl;
79 u32 clk_duty_meas_res;
81 /* The next registers are not key-protected */
88 u32 d_pll_ext_param[3];
89 u32 d2_pll_ext_param[3];
98 u32 reloc_ctrl_decode[2];
100 u32 shared_sram_decode[2];
109 * ast_get_clk() - get a pointer to Clock Driver
111 * @devp, OUT - pointer to Clock Driver
112 * @return zero on success, error code (< 0) otherwise.
114 int ast_get_clk(struct udevice **devp);
117 * ast_get_scu() - get a pointer to SCU registers
119 * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise
121 void *ast_get_scu(void);
123 #endif /* __ASSEMBLY__ */
125 #endif /* _ASM_ARCH_SCU_AST2500_H */