3 * eInfochips Ltd. <www.einfochips.com>
4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
7 * Marvell Semiconductor <www.marvell.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 #ifndef __ARMADA100_SPI_H_
29 #define __ARMADA100_SPI_H_
31 #include <asm/arch/armada100.h>
33 #define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
34 #define SSP_REG_BASE(x) CAT_BASE_ADDR(x)
37 * SSP Serial Port Registers
41 u32 sscr0; /* SSP Control Register 0 - 0x000 */
42 u32 sscr1; /* SSP Control Register 1 - 0x004 */
43 u32 sssr; /* SSP Status Register - 0x008 */
44 u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
45 u32 ssdr; /* SSP Data Register - 0x010 */
47 u32 ssto; /* SSP Timeout Register - 0x028 */
48 u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
49 u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
50 u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
51 u32 sstss; /* SSP Timeslot Status Register - 0x038 */
54 #define DEFAULT_WORD_LEN 8
55 #define SSP_FLUSH_NUM 0x2000
56 #define RX_THRESH_DEF 8
57 #define TX_THRESH_DEF 8
58 #define TIMEOUT_DEF 1000
60 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
61 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
62 #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
63 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity
65 #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
66 #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
67 #define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
68 #define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
70 #define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
71 #define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
72 #define SSCR1_TINTE (1 << 19) /* Receiver Time-out
75 #define SSCR0_DSS 0x0f /* Data Size Select (mask) */
76 #define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
77 #define SSCR0_FRF 0x30 /* FRame Format (mask) */
78 #define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
79 Peripheral Interface */
80 #define SSCR0_TI (0x1 << 4) /* TI's Synchronous
81 Serial Protocol (SSP) */
82 #define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
83 #define SSCR0_ECS (1 << 6) /* External clock select */
84 #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port
87 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
88 #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
89 #define SSSR_BSY (1 << 4) /* SSP Busy */
90 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
91 #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
92 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
93 #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
95 #endif /* __ARMADA100_SPI_H_ */