3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 * Contributor: Mahavir Jain <mjain@marvell.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
26 #ifndef _ASM_ARCH_ARMADA100_H
27 #define _ASM_ARCH_ARMADA100_H
30 #include <asm/types.h>
32 #endif /* __ASSEMBLY__ */
34 #if defined (CONFIG_ARMADA100)
35 #include <asm/arch/cpu.h>
37 /* Common APB clock register bit definitions */
38 #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
39 #define APBC_FNCLK (1<<1) /* Functional Clock Enable */
40 #define APBC_RST (1<<2) /* Reset Generation */
41 /* Functional Clock Selection Mask */
42 #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
44 /* Fast Ethernet Controller Clock register definition */
45 #define FE_CLK_RST 0x1
46 #define FE_CLK_ENA 0x8
48 /* SSP2 Clock Control */
49 #define SSP2_APBCLK 0x01
50 #define SSP2_FNCLK 0x02
52 /* Register Base Addresses */
53 #define ARMD1_DRAM_BASE 0xB0000000
54 #define ARMD1_FEC_BASE 0xC0800000
55 #define ARMD1_TIMER_BASE 0xD4014000
56 #define ARMD1_APBC1_BASE 0xD4015000
57 #define ARMD1_APBC2_BASE 0xD4015800
58 #define ARMD1_UART1_BASE 0xD4017000
59 #define ARMD1_UART2_BASE 0xD4018000
60 #define ARMD1_GPIO_BASE 0xD4019000
61 #define ARMD1_SSP1_BASE 0xD401B000
62 #define ARMD1_SSP2_BASE 0xD401C000
63 #define ARMD1_MFPR_BASE 0xD401E000
64 #define ARMD1_SSP3_BASE 0xD401F000
65 #define ARMD1_SSP4_BASE 0xD4020000
66 #define ARMD1_SSP5_BASE 0xD4021000
67 #define ARMD1_UART3_BASE 0xD4026000
68 #define ARMD1_MPMU_BASE 0xD4050000
69 #define ARMD1_APMU_BASE 0xD4282800
70 #define ARMD1_CPU_BASE 0xD4282C00
73 * Main Power Management (MPMU) Registers
74 * Refer Datasheet Appendix A.8
76 struct armd1mpmu_registers {
82 u8 pad1[0x030 - 0x014 - 4];
84 u8 pad2[0x200 - 0x030 - 4];
85 u32 wdtpcr; /*0x0200*/
86 u8 pad3[0x1000 - 0x200 - 4];
89 u8 pad4[0x1020 - 0x1004 - 4];
96 * Application Subsystem Power Management
97 * Refer Datasheet Appendix A.9
99 struct armd1apmu_registers {
103 u32 ccsr; /* 0x00C */
104 u32 fc_timer; /* 0x010 */
106 u32 ideal_cfg; /* 0x018 */
107 u8 pad3[0x04C - 0x018 - 4];
108 u32 lcdcrc; /* 0x04C */
109 u32 cciccrc; /* 0x050 */
110 u32 sd1crc; /* 0x054 */
111 u32 sd2crc; /* 0x058 */
112 u32 usbcrc; /* 0x05C */
113 u32 nfccrc; /* 0x060 */
114 u32 dmacrc; /* 0x064 */
116 u32 buscrc; /* 0x06C */
117 u8 pad5[0x07C - 0x06C - 4];
118 u32 wake_clr; /* 0x07C */
119 u8 pad6[0x090 - 0x07C - 4];
120 u32 core_status; /* 0x090 */
121 u32 rfsc; /* 0x094 */
123 u32 irwc; /* 0x09C */
125 u8 pad7[0x0B0 - 0x0A0 - 4];
126 u32 mhst; /* 0x0B0 */
128 u8 pad8[0x0C0 - 0x0B4 - 4];
129 u32 msst; /* 0x0C0 */
130 u32 pllss; /* 0x0C4 */
132 u32 gccrc; /* 0x0CC */
133 u8 pad9[0x0D4 - 0x0CC - 4];
134 u32 smccrc; /* 0x0D4 */
136 u32 xdcrc; /* 0x0DC */
137 u32 sd3crc; /* 0x0E0 */
138 u32 sd4crc; /* 0x0E4 */
139 u8 pad11[0x0F0 - 0x0E4 - 4];
140 u32 cfcrc; /* 0x0F0 */
141 u32 mspcrc; /* 0x0F4 */
142 u32 cmucrc; /* 0x0F8 */
143 u32 fecrc; /* 0x0FC */
144 u32 pciecrc; /* 0x100 */
145 u32 epdcrc; /* 0x104 */
149 * APB1 Clock Reset/Control Registers
150 * Refer Datasheet Appendix A.10
152 struct armd1apb1_registers {
160 u8 pad0[0x028 - 0x018 - 4];
164 u32 timers; /*0x034*/
165 u8 pad1[0x03c - 0x034 - 4];
167 u32 sw_jtag; /*0x040*/
168 u32 timer1; /*0x044*/
169 u32 onewire; /*0x048*/
170 u8 pad2[0x050 - 0x048 - 4];
171 u32 asfar; /*0x050 AIB Secure First Access Reg*/
172 u32 assar; /*0x054 AIB Secure Second Access Reg*/
173 u8 pad3[0x06c - 0x054 - 4];
176 u8 pad4[0x07c - 0x070 - 4];
177 u32 timer2; /*0x07C*/
178 u8 pad5[0x084 - 0x07c - 4];
183 * APB2 Clock Reset/Control Registers
184 * Refer Datasheet Appendix A.11
186 struct armd1apb2_registers {
187 u32 pad1[0x01C - 0x000];
188 u32 ssp1_clkrst; /* 0x01C */
189 u32 ssp2_clkrst; /* 0x020 */
190 u32 pad2[0x04C - 0x020 - 4];
191 u32 ssp3_clkrst; /* 0x04C */
192 u32 pad3[0x058 - 0x04C - 4];
193 u32 ssp4_clkrst; /* 0x058 */
194 u32 ssp5_clkrst; /* 0x05C */
197 #endif /* CONFIG_ARMADA100 */
198 #endif /* _ASM_ARCH_ARMADA100_H */