3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 * Contributor: Mahavir Jain <mjain@marvell.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
26 #ifndef _ASM_ARCH_ARMADA100_H
27 #define _ASM_ARCH_ARMADA100_H
30 #include <asm/types.h>
32 #endif /* __ASSEMBLY__ */
34 #if defined (CONFIG_ARMADA100)
35 #include <asm/arch/cpu.h>
37 /* Common APB clock register bit definitions */
38 #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
39 #define APBC_FNCLK (1<<1) /* Functional Clock Enable */
40 #define APBC_RST (1<<2) /* Reset Generation */
41 /* Functional Clock Selection Mask */
42 #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
44 /* Register Base Addresses */
45 #define ARMD1_DRAM_BASE 0xB0000000
46 #define ARMD1_TIMER_BASE 0xD4014000
47 #define ARMD1_APBC1_BASE 0xD4015000
48 #define ARMD1_APBC2_BASE 0xD4015800
49 #define ARMD1_UART1_BASE 0xD4017000
50 #define ARMD1_UART2_BASE 0xD4018000
51 #define ARMD1_GPIO_BASE 0xD4019000
52 #define ARMD1_SSP1_BASE 0xD401B000
53 #define ARMD1_SSP2_BASE 0xD401C000
54 #define ARMD1_MFPR_BASE 0xD401E000
55 #define ARMD1_SSP3_BASE 0xD401F000
56 #define ARMD1_SSP4_BASE 0xD4020000
57 #define ARMD1_SSP5_BASE 0xD4021000
58 #define ARMD1_UART3_BASE 0xD4026000
59 #define ARMD1_MPMU_BASE 0xD4050000
60 #define ARMD1_APMU_BASE 0xD4282800
61 #define ARMD1_CPU_BASE 0xD4282C00
64 * Main Power Management (MPMU) Registers
65 * Refer Datasheet Appendix A.8
67 struct armd1mpmu_registers {
73 u8 pad1[0x030 - 0x014 - 4];
75 u8 pad2[0x200 - 0x030 - 4];
76 u32 wdtpcr; /*0x0200*/
77 u8 pad3[0x1000 - 0x200 - 4];
80 u8 pad4[0x1020 - 0x1004 - 4];
87 * APB1 Clock Reset/Control Registers
88 * Refer Datasheet Appendix A.10
90 struct armd1apb1_registers {
98 u8 pad0[0x028 - 0x018 - 4];
102 u32 timers; /*0x034*/
103 u8 pad1[0x03c - 0x034 - 4];
105 u32 sw_jtag; /*0x040*/
106 u32 timer1; /*0x044*/
107 u32 onewire; /*0x048*/
108 u8 pad2[0x050 - 0x048 - 4];
109 u32 asfar; /*0x050 AIB Secure First Access Reg*/
110 u32 assar; /*0x054 AIB Secure Second Access Reg*/
111 u8 pad3[0x06c - 0x054 - 4];
114 u8 pad4[0x07c - 0x070 - 4];
115 u32 timer2; /*0x07C*/
116 u8 pad5[0x084 - 0x07c - 4];
120 #endif /* CONFIG_ARMADA100 */
121 #endif /* _ASM_ARCH_ARMADA100_H */