3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 * Contributor: Mahavir Jain <mjain@marvell.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
26 #ifndef _ASM_ARCH_ARMADA100_H
27 #define _ASM_ARCH_ARMADA100_H
29 #if defined (CONFIG_ARMADA100)
31 /* Common APB clock register bit definitions */
32 #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
33 #define APBC_FNCLK (1<<1) /* Functional Clock Enable */
34 #define APBC_RST (1<<2) /* Reset Generation */
35 /* Functional Clock Selection Mask */
36 #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
38 /* Fast Ethernet Controller Clock register definition */
39 #define FE_CLK_RST 0x1
40 #define FE_CLK_ENA 0x8
42 /* SSP2 Clock Control */
43 #define SSP2_APBCLK 0x01
44 #define SSP2_FNCLK 0x02
46 /* USB Clock/reset control bits */
47 #define USB_SPH_AXICLK_EN 0x10
48 #define USB_SPH_AXI_RST 0x02
51 #define APB2_26M_EN (1 << 20)
52 #define AP_26M (1 << 4)
54 /* Register Base Addresses */
55 #define ARMD1_DRAM_BASE 0xB0000000
56 #define ARMD1_FEC_BASE 0xC0800000
57 #define ARMD1_TIMER_BASE 0xD4014000
58 #define ARMD1_APBC1_BASE 0xD4015000
59 #define ARMD1_APBC2_BASE 0xD4015800
60 #define ARMD1_UART1_BASE 0xD4017000
61 #define ARMD1_UART2_BASE 0xD4018000
62 #define ARMD1_GPIO_BASE 0xD4019000
63 #define ARMD1_SSP1_BASE 0xD401B000
64 #define ARMD1_SSP2_BASE 0xD401C000
65 #define ARMD1_MFPR_BASE 0xD401E000
66 #define ARMD1_SSP3_BASE 0xD401F000
67 #define ARMD1_SSP4_BASE 0xD4020000
68 #define ARMD1_SSP5_BASE 0xD4021000
69 #define ARMD1_UART3_BASE 0xD4026000
70 #define ARMD1_MPMU_BASE 0xD4050000
71 #define ARMD1_USB_HOST_BASE 0xD4209000
72 #define ARMD1_APMU_BASE 0xD4282800
73 #define ARMD1_CPU_BASE 0xD4282C00
75 #endif /* CONFIG_ARMADA100 */
76 #endif /* _ASM_ARCH_ARMADA100_H */