4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef MMC_HOST_DEF_H
17 #define MMC_HOST_DEF_H
20 * OMAP HSMMC register definitions
22 #define OMAP_HSMMC1_BASE 0x48060100
23 #define OMAP_HSMMC2_BASE 0x481D8100
25 typedef struct hsmmc {
26 unsigned char res1[0x10];
27 unsigned int sysconfig; /* 0x10 */
28 unsigned int sysstatus; /* 0x14 */
29 unsigned char res2[0x14];
30 unsigned int con; /* 0x2C */
31 unsigned char res3[0xD4];
32 unsigned int blk; /* 0x104 */
33 unsigned int arg; /* 0x108 */
34 unsigned int cmd; /* 0x10C */
35 unsigned int rsp10; /* 0x110 */
36 unsigned int rsp32; /* 0x114 */
37 unsigned int rsp54; /* 0x118 */
38 unsigned int rsp76; /* 0x11C */
39 unsigned int data; /* 0x120 */
40 unsigned int pstate; /* 0x124 */
41 unsigned int hctl; /* 0x128 */
42 unsigned int sysctl; /* 0x12C */
43 unsigned int stat; /* 0x130 */
44 unsigned int ie; /* 0x134 */
45 unsigned char res4[0x8];
46 unsigned int capa; /* 0x140 */
50 * OMAP HS MMC Bit definitions
52 #define MMC_SOFTRESET (0x1 << 1)
53 #define RESETDONE (0x1 << 0)
54 #define NOOPENDRAIN (0x0 << 0)
55 #define OPENDRAIN (0x1 << 0)
57 #define INIT_NOINIT (0x0 << 1)
58 #define INIT_INITSTREAM (0x1 << 1)
59 #define HR_NOHOSTRESP (0x0 << 2)
60 #define STR_BLOCK (0x0 << 3)
61 #define MODE_FUNC (0x0 << 4)
62 #define DW8_1_4BITMODE (0x0 << 5)
63 #define MIT_CTO (0x0 << 6)
64 #define CDP_ACTIVEHIGH (0x0 << 7)
65 #define WPP_ACTIVEHIGH (0x0 << 8)
66 #define RESERVED_MASK (0x3 << 9)
67 #define CTPL_MMC_SD (0x0 << 11)
68 #define BLEN_512BYTESLEN (0x200 << 0)
69 #define NBLK_STPCNT (0x0 << 16)
70 #define DE_DISABLE (0x0 << 0)
71 #define BCE_DISABLE (0x0 << 1)
72 #define BCE_ENABLE (0x1 << 1)
73 #define ACEN_DISABLE (0x0 << 2)
74 #define DDIR_OFFSET (4)
75 #define DDIR_MASK (0x1 << 4)
76 #define DDIR_WRITE (0x0 << 4)
77 #define DDIR_READ (0x1 << 4)
78 #define MSBS_SGLEBLK (0x0 << 5)
79 #define MSBS_MULTIBLK (0x1 << 5)
80 #define RSP_TYPE_OFFSET (16)
81 #define RSP_TYPE_MASK (0x3 << 16)
82 #define RSP_TYPE_NORSP (0x0 << 16)
83 #define RSP_TYPE_LGHT136 (0x1 << 16)
84 #define RSP_TYPE_LGHT48 (0x2 << 16)
85 #define RSP_TYPE_LGHT48B (0x3 << 16)
86 #define CCCE_NOCHECK (0x0 << 19)
87 #define CCCE_CHECK (0x1 << 19)
88 #define CICE_NOCHECK (0x0 << 20)
89 #define CICE_CHECK (0x1 << 20)
90 #define DP_OFFSET (21)
91 #define DP_MASK (0x1 << 21)
92 #define DP_NO_DATA (0x0 << 21)
93 #define DP_DATA (0x1 << 21)
94 #define CMD_TYPE_NORMAL (0x0 << 22)
95 #define INDEX_OFFSET (24)
96 #define INDEX_MASK (0x3f << 24)
97 #define INDEX(i) (i << 24)
98 #define DATI_MASK (0x1 << 1)
99 #define CMDI_MASK (0x1 << 0)
100 #define DTW_1_BITMODE (0x0 << 1)
101 #define DTW_4_BITMODE (0x1 << 1)
102 #define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
103 #define SDBP_PWROFF (0x0 << 8)
104 #define SDBP_PWRON (0x1 << 8)
105 #define SDVS_1V8 (0x5 << 9)
106 #define SDVS_3V0 (0x6 << 9)
107 #define ICE_MASK (0x1 << 0)
108 #define ICE_STOP (0x0 << 0)
109 #define ICS_MASK (0x1 << 1)
110 #define ICS_NOTREADY (0x0 << 1)
111 #define ICE_OSCILLATE (0x1 << 0)
112 #define CEN_MASK (0x1 << 2)
113 #define CEN_DISABLE (0x0 << 2)
114 #define CEN_ENABLE (0x1 << 2)
115 #define CLKD_OFFSET (6)
116 #define CLKD_MASK (0x3FF << 6)
117 #define DTO_MASK (0xF << 16)
118 #define DTO_15THDTO (0xE << 16)
119 #define SOFTRESETALL (0x1 << 24)
120 #define CC_MASK (0x1 << 0)
121 #define TC_MASK (0x1 << 1)
122 #define BWR_MASK (0x1 << 4)
123 #define BRR_MASK (0x1 << 5)
124 #define ERRI_MASK (0x1 << 15)
125 #define IE_CC (0x01 << 0)
126 #define IE_TC (0x01 << 1)
127 #define IE_BWR (0x01 << 4)
128 #define IE_BRR (0x01 << 5)
129 #define IE_CTO (0x01 << 16)
130 #define IE_CCRC (0x01 << 17)
131 #define IE_CEB (0x01 << 18)
132 #define IE_CIE (0x01 << 19)
133 #define IE_DTO (0x01 << 20)
134 #define IE_DCRC (0x01 << 21)
135 #define IE_DEB (0x01 << 22)
136 #define IE_CERR (0x01 << 28)
137 #define IE_BADA (0x01 << 29)
139 #define VS30_3V0SUP (1 << 25)
140 #define VS18_1V8SUP (1 << 26)
142 /* Driver definitions */
143 #define MMCSD_SECTOR_SIZE 512
147 #define SECTOR_MODE 1
148 #define CLK_INITSEQ 0
152 #define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
153 #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
155 /* Clock Configurations and Macros */
156 #define MMC_CLOCK_REFERENCE 96 /* MHz */
158 #define mmc_reg_out(addr, mask, val)\
159 writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
161 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
163 #endif /* MMC_HOST_DEF_H */