4 * hardware specific header
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
19 #ifndef __AM33XX_HARDWARE_H
20 #define __AM33XX_HARDWARE_H
22 #include <asm/arch/omap.h>
24 /* Module base addresses */
25 #define UART0_BASE 0x44E09000
27 /* DM Timer base addresses */
28 #define DM_TIMER0_BASE 0x4802C000
29 #define DM_TIMER1_BASE 0x4802E000
30 #define DM_TIMER2_BASE 0x48040000
31 #define DM_TIMER3_BASE 0x48042000
32 #define DM_TIMER4_BASE 0x48044000
33 #define DM_TIMER5_BASE 0x48046000
34 #define DM_TIMER6_BASE 0x48048000
35 #define DM_TIMER7_BASE 0x4804A000
37 /* GPIO Base address */
38 #define GPIO0_BASE 0x48032000
39 #define GPIO1_BASE 0x4804C000
40 #define GPIO2_BASE 0x481AC000
42 /* BCH Error Location Module */
43 #define ELM_BASE 0x48080000
46 #define WDT_BASE 0x44E35000
48 /* Control Module Base Address */
49 #define CTRL_BASE 0x44E10000
50 #define CTRL_DEVICE_BASE 0x44E10600
52 /* PRCM Base Address */
53 #define PRCM_BASE 0x44E00000
55 /* EMIF Base address */
56 #define EMIF4_0_CFG_BASE 0x4C000000
57 #define EMIF4_1_CFG_BASE 0x4D000000
59 /* PLL related registers */
60 #define CM_PER 0x44E00000
61 #define CM_WKUP 0x44E00400
62 #define CM_DPLL 0x44E00500
63 #define CM_DEVICE 0x44E00700
64 #define CM_RTC 0x44E00800
65 #define CM_CEFUSE 0x44E00A00
66 #define PRM_DEVICE 0x44E00F00
68 /* VTP Base address */
69 #define VTP0_CTRL_ADDR 0x44E10E0C
71 /* DDR Base address */
72 #define DDR_CTRL_ADDR 0x44E10E04
73 #define DDR_CONTROL_BASE_ADDR 0x44E11404
74 #define DDR_PHY_BASE_ADDR 0x44E12000
75 #define DDR_PHY_BASE_ADDR2 0x44E120A4
78 #define DEFAULT_UART_BASE UART0_BASE
80 #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
81 #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
83 /* GPMC Base address */
84 #define GPMC_BASE 0x50000000
86 /* CPSW Config space */
87 #define AM335X_CPSW_BASE 0x4A100000
88 #define AM335X_CPSW_MDIO_BASE 0x4A101000
90 /* RTC base address */
91 #define AM335X_RTC_BASE 0x44E3E000
94 #define AM335X_USB0_OTG_BASE 0x47401000
95 #define AM335X_USB1_OTG_BASE 0x47401800
97 #endif /* __AM33XX_HARDWARE_H */