6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
22 #include <asm/arch/hardware.h>
25 /* AM335X EMIF Register values */
26 #define VTP_CTRL_READY (0x1 << 5)
27 #define VTP_CTRL_ENABLE (0x1 << 6)
28 #define VTP_CTRL_START_EN (0x1)
29 #define PHY_DLL_LOCK_DIFF 0x0
30 #define DDR_CKE_CTRL_NORMAL 0x1
32 #define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
33 #define DDR2_EMIF_TIM1 0x0666B3C9
34 #define DDR2_EMIF_TIM2 0x243631CA
35 #define DDR2_EMIF_TIM3 0x0000033F
36 #define DDR2_EMIF_SDCFG 0x41805332
37 #define DDR2_EMIF_SDREF 0x0000081a
38 #define DDR2_DLL_LOCK_DIFF 0x0
39 #define DDR2_RATIO 0x80
40 #define DDR2_INVERT_CLKOUT 0x00
41 #define DDR2_RD_DQS 0x12
42 #define DDR2_WR_DQS 0x00
43 #define DDR2_PHY_WRLVL 0x00
44 #define DDR2_PHY_GATELVL 0x00
45 #define DDR2_PHY_WR_DATA 0x40
46 #define DDR2_PHY_FIFO_WE 0x80
47 #define DDR2_PHY_RANK0_DELAY 0x1
48 #define DDR2_IOCTRL_VALUE 0x18B
53 void config_sdram(const struct emif_regs *regs);
58 void set_sdram_timings(const struct emif_regs *regs);
63 void config_ddr_phy(const struct emif_regs *regs);
66 * This structure represents the DDR registers on AM33XX devices.
67 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
68 * correspond to DATA1 registers defined here.
71 unsigned int resv0[7];
72 unsigned int cm0csratio; /* offset 0x01C */
73 unsigned int resv1[2];
74 unsigned int cm0dldiff; /* offset 0x028 */
75 unsigned int cm0iclkout; /* offset 0x02C */
76 unsigned int resv2[8];
77 unsigned int cm1csratio; /* offset 0x050 */
78 unsigned int resv3[2];
79 unsigned int cm1dldiff; /* offset 0x05C */
80 unsigned int cm1iclkout; /* offset 0x060 */
81 unsigned int resv4[8];
82 unsigned int cm2csratio; /* offset 0x084 */
83 unsigned int resv5[2];
84 unsigned int cm2dldiff; /* offset 0x090 */
85 unsigned int cm2iclkout; /* offset 0x094 */
86 unsigned int resv6[12];
87 unsigned int dt0rdsratio0; /* offset 0x0C8 */
88 unsigned int resv7[4];
89 unsigned int dt0wdsratio0; /* offset 0x0DC */
90 unsigned int resv8[4];
91 unsigned int dt0wiratio0; /* offset 0x0F0 */
93 unsigned int dt0wimode0; /* offset 0x0F8 */
94 unsigned int dt0giratio0; /* offset 0x0FC */
96 unsigned int dt0gimode0; /* offset 0x104 */
97 unsigned int dt0fwsratio0; /* offset 0x108 */
98 unsigned int resv11[4];
99 unsigned int dt0dqoffset; /* offset 0x11C */
100 unsigned int dt0wrsratio0; /* offset 0x120 */
101 unsigned int resv12[4];
102 unsigned int dt0rdelays0; /* offset 0x134 */
103 unsigned int dt0dldiff0; /* offset 0x138 */
107 * Encapsulates DDR CMD control registers.
110 unsigned long cmd0csratio;
111 unsigned long cmd0csforce;
112 unsigned long cmd0csdelay;
113 unsigned long cmd0dldiff;
114 unsigned long cmd0iclkout;
115 unsigned long cmd1csratio;
116 unsigned long cmd1csforce;
117 unsigned long cmd1csdelay;
118 unsigned long cmd1dldiff;
119 unsigned long cmd1iclkout;
120 unsigned long cmd2csratio;
121 unsigned long cmd2csforce;
122 unsigned long cmd2csdelay;
123 unsigned long cmd2dldiff;
124 unsigned long cmd2iclkout;
128 * Encapsulates DDR DATA registers.
131 unsigned long datardsratio0;
132 unsigned long datawdsratio0;
133 unsigned long datawiratio0;
134 unsigned long datagiratio0;
135 unsigned long datafwsratio0;
136 unsigned long datawrsratio0;
137 unsigned long datauserank0delay;
138 unsigned long datadldiff0;
142 * Configure DDR CMD control registers
144 void config_cmd_ctrl(const struct cmd_control *cmd);
147 * Configure DDR DATA registers
149 void config_ddr_data(int data_macrono, const struct ddr_data *data);
152 * This structure represents the DDR io control on AM33XX devices.
154 struct ddr_cmdtctrl {
155 unsigned int resv1[1];
156 unsigned int cm0ioctl;
157 unsigned int cm1ioctl;
158 unsigned int cm2ioctl;
159 unsigned int resv2[12];
160 unsigned int dt0ioctl;
161 unsigned int dt1ioctl;
165 * Configure DDR io control registers
167 void config_io_ctrl(unsigned long val);
170 unsigned int ddrioctrl;
171 unsigned int resv1[325];
172 unsigned int ddrckectrl;
175 void config_ddr(short ddr_type);
177 #endif /* _DDR_DEFS_H */