6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/hardware.h>
17 /* AM335X EMIF Register values */
18 #define VTP_CTRL_READY (0x1 << 5)
19 #define VTP_CTRL_ENABLE (0x1 << 6)
20 #define VTP_CTRL_START_EN (0x1)
22 #define DDR_CKE_CTRL_NORMAL 0x3
24 #define DDR_CKE_CTRL_NORMAL 0x1
26 #define PHY_EN_DYN_PWRDN (0x1 << 20)
28 /* Micron MT47H128M16RT-25E */
29 #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
30 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
31 #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
32 #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
33 #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
34 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
35 #define MT47H128M16RT25E_RATIO 0x80
36 #define MT47H128M16RT25E_RD_DQS 0x12
37 #define MT47H128M16RT25E_PHY_WR_DATA 0x40
38 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80
39 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
41 /* Micron MT41J128M16JT-125 */
42 #define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
43 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B
44 #define MT41J128MJT125_EMIF_TIM2 0x26337FDA
45 #define MT41J128MJT125_EMIF_TIM3 0x501F830F
46 #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
47 #define MT41J128MJT125_EMIF_SDREF 0x0000093B
48 #define MT41J128MJT125_ZQ_CFG 0x50074BE4
49 #define MT41J128MJT125_RATIO 0x40
50 #define MT41J128MJT125_INVERT_CLKOUT 0x1
51 #define MT41J128MJT125_RD_DQS 0x3B
52 #define MT41J128MJT125_WR_DQS 0x85
53 #define MT41J128MJT125_PHY_WR_DATA 0xC1
54 #define MT41J128MJT125_PHY_FIFO_WE 0x100
55 #define MT41J128MJT125_IOCTRL_VALUE 0x18B
57 /* Micron MT41K128M16JT-187E */
58 #define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
59 #define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
60 #define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
61 #define MT41K128MJT187E_EMIF_TIM3 0x501F830F
62 #define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
63 #define MT41K128MJT187E_EMIF_SDREF 0x0000093B
64 #define MT41K128MJT187E_ZQ_CFG 0x50074BE4
65 #define MT41K128MJT187E_RATIO 0x40
66 #define MT41K128MJT187E_INVERT_CLKOUT 0x1
67 #define MT41K128MJT187E_RD_DQS 0x3B
68 #define MT41K128MJT187E_WR_DQS 0x85
69 #define MT41K128MJT187E_PHY_WR_DATA 0xC1
70 #define MT41K128MJT187E_PHY_FIFO_WE 0x100
71 #define MT41K128MJT187E_IOCTRL_VALUE 0x18B
73 /* Micron MT41J64M16JT-125 */
74 #define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
76 /* Micron MT41J256M16JT-125 */
77 #define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
79 /* Micron MT41J256M8HX-15E */
80 #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006
81 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
82 #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
83 #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
84 #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
85 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
86 #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
87 #define MT41J256M8HX15E_RATIO 0x40
88 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1
89 #define MT41J256M8HX15E_RD_DQS 0x3B
90 #define MT41J256M8HX15E_WR_DQS 0x85
91 #define MT41J256M8HX15E_PHY_WR_DATA 0xC1
92 #define MT41J256M8HX15E_PHY_FIFO_WE 0x100
93 #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
95 /* Micron MT41K256M16HA-125E */
96 #define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
97 #define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
98 #define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
99 #define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
100 #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
101 #define MT41K256M16HA125E_EMIF_SDREF 0xC30
102 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
103 #define MT41K256M16HA125E_RATIO 0x80
104 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0
105 #define MT41K256M16HA125E_RD_DQS 0x38
106 #define MT41K256M16HA125E_WR_DQS 0x44
107 #define MT41K256M16HA125E_PHY_WR_DATA 0x7D
108 #define MT41K256M16HA125E_PHY_FIFO_WE 0x94
109 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
111 /* Micron MT41J512M8RH-125 on EVM v1.5 */
112 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
113 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
114 #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
115 #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
116 #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
117 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B
118 #define MT41J512M8RH125_ZQ_CFG 0x50074BE4
119 #define MT41J512M8RH125_RATIO 0x80
120 #define MT41J512M8RH125_INVERT_CLKOUT 0x0
121 #define MT41J512M8RH125_RD_DQS 0x3B
122 #define MT41J512M8RH125_WR_DQS 0x3C
123 #define MT41J512M8RH125_PHY_FIFO_WE 0xA5
124 #define MT41J512M8RH125_PHY_WR_DATA 0x74
125 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B
127 /* Samsung K4B2G1646E-BIH9 */
128 #define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007
129 #define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
130 #define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
131 #define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
132 #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
133 #define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
134 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
135 #define K4B2G1646EBIH9_RATIO 0x80
136 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
137 #define K4B2G1646EBIH9_RD_DQS 0x35
138 #define K4B2G1646EBIH9_WR_DQS 0x3A
139 #define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
140 #define K4B2G1646EBIH9_PHY_WR_DATA 0x76
141 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
143 #define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
144 #define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
145 #define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
146 #define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
147 #define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
148 #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
149 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
151 #define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
152 #define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
153 #define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
154 #define DDR3_DATA0_IOCTRL_VALUE 0x84
155 #define DDR3_DATA1_IOCTRL_VALUE 0x84
156 #define DDR3_DATA2_IOCTRL_VALUE 0x84
157 #define DDR3_DATA3_IOCTRL_VALUE 0x84
162 void config_dmm(const struct dmm_lisa_map_regs *regs);
167 void config_sdram(const struct emif_regs *regs, int nr);
168 void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
173 void set_sdram_timings(const struct emif_regs *regs, int nr);
178 void config_ddr_phy(const struct emif_regs *regs, int nr);
180 struct ddr_cmd_regs {
181 unsigned int resv0[7];
182 unsigned int cm0csratio; /* offset 0x01C */
183 unsigned int resv1[3];
184 unsigned int cm0iclkout; /* offset 0x02C */
185 unsigned int resv2[8];
186 unsigned int cm1csratio; /* offset 0x050 */
187 unsigned int resv3[3];
188 unsigned int cm1iclkout; /* offset 0x060 */
189 unsigned int resv4[8];
190 unsigned int cm2csratio; /* offset 0x084 */
191 unsigned int resv5[3];
192 unsigned int cm2iclkout; /* offset 0x094 */
193 unsigned int resv6[3];
196 struct ddr_data_regs {
197 unsigned int dt0rdsratio0; /* offset 0x0C8 */
198 unsigned int resv1[4];
199 unsigned int dt0wdsratio0; /* offset 0x0DC */
200 unsigned int resv2[4];
201 unsigned int dt0wiratio0; /* offset 0x0F0 */
203 unsigned int dt0wimode0; /* offset 0x0F8 */
204 unsigned int dt0giratio0; /* offset 0x0FC */
206 unsigned int dt0gimode0; /* offset 0x104 */
207 unsigned int dt0fwsratio0; /* offset 0x108 */
208 unsigned int resv5[4];
209 unsigned int dt0dqoffset; /* offset 0x11C */
210 unsigned int dt0wrsratio0; /* offset 0x120 */
211 unsigned int resv6[4];
212 unsigned int dt0rdelays0; /* offset 0x134 */
213 unsigned int dt0dldiff0; /* offset 0x138 */
214 unsigned int resv7[12];
218 * This structure represents the DDR registers on AM33XX devices.
219 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
220 * correspond to DATA1 registers defined here.
223 unsigned int resv0[3];
224 unsigned int cm0config; /* offset 0x00C */
225 unsigned int cm0configclk; /* offset 0x010 */
226 unsigned int resv1[2];
227 unsigned int cm0csratio; /* offset 0x01C */
228 unsigned int resv2[3];
229 unsigned int cm0iclkout; /* offset 0x02C */
230 unsigned int resv3[4];
231 unsigned int cm1config; /* offset 0x040 */
232 unsigned int cm1configclk; /* offset 0x044 */
233 unsigned int resv4[2];
234 unsigned int cm1csratio; /* offset 0x050 */
235 unsigned int resv5[3];
236 unsigned int cm1iclkout; /* offset 0x060 */
237 unsigned int resv6[4];
238 unsigned int cm2config; /* offset 0x074 */
239 unsigned int cm2configclk; /* offset 0x078 */
240 unsigned int resv7[2];
241 unsigned int cm2csratio; /* offset 0x084 */
242 unsigned int resv8[3];
243 unsigned int cm2iclkout; /* offset 0x094 */
244 unsigned int resv9[12];
245 unsigned int dt0rdsratio0; /* offset 0x0C8 */
246 unsigned int resv10[4];
247 unsigned int dt0wdsratio0; /* offset 0x0DC */
248 unsigned int resv11[4];
249 unsigned int dt0wiratio0; /* offset 0x0F0 */
251 unsigned int dt0wimode0; /* offset 0x0F8 */
252 unsigned int dt0giratio0; /* offset 0x0FC */
254 unsigned int dt0gimode0; /* offset 0x104 */
255 unsigned int dt0fwsratio0; /* offset 0x108 */
256 unsigned int resv14[4];
257 unsigned int dt0dqoffset; /* offset 0x11C */
258 unsigned int dt0wrsratio0; /* offset 0x120 */
259 unsigned int resv15[4];
260 unsigned int dt0rdelays0; /* offset 0x134 */
261 unsigned int dt0dldiff0; /* offset 0x138 */
265 * Encapsulates DDR CMD control registers.
268 unsigned long cmd0csratio;
269 unsigned long cmd0csforce;
270 unsigned long cmd0csdelay;
271 unsigned long cmd0iclkout;
272 unsigned long cmd1csratio;
273 unsigned long cmd1csforce;
274 unsigned long cmd1csdelay;
275 unsigned long cmd1iclkout;
276 unsigned long cmd2csratio;
277 unsigned long cmd2csforce;
278 unsigned long cmd2csdelay;
279 unsigned long cmd2iclkout;
283 * Encapsulates DDR DATA registers.
286 unsigned long datardsratio0;
287 unsigned long datawdsratio0;
288 unsigned long datawiratio0;
289 unsigned long datagiratio0;
290 unsigned long datafwsratio0;
291 unsigned long datawrsratio0;
295 * Configure DDR CMD control registers
297 void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
300 * Configure DDR DATA registers
302 void config_ddr_data(const struct ddr_data *data, int nr);
305 * This structure represents the DDR io control on AM33XX devices.
307 struct ddr_cmdtctrl {
308 unsigned int cm0ioctl;
309 unsigned int cm1ioctl;
310 unsigned int cm2ioctl;
311 unsigned int resv2[12];
312 unsigned int dt0ioctl;
313 unsigned int dt1ioctl;
314 unsigned int dt2ioctrl;
315 unsigned int dt3ioctrl;
316 unsigned int resv3[4];
317 unsigned int emif_sdram_config_ext;
321 unsigned int cm0ioctl;
322 unsigned int cm1ioctl;
323 unsigned int cm2ioctl;
324 unsigned int dt0ioctl;
325 unsigned int dt1ioctl;
326 unsigned int dt2ioctrl;
327 unsigned int dt3ioctrl;
328 unsigned int emif_sdram_config_ext;
332 * Configure DDR io control registers
334 void config_io_ctrl(const struct ctrl_ioregs *ioregs);
337 unsigned int ddrioctrl;
338 unsigned int resv1[325];
339 unsigned int ddrckectrl;
342 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
343 const struct ddr_data *data, const struct cmd_control *ctrl,
344 const struct emif_regs *regs, int nr);
345 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
347 #endif /* _DDR_DEFS_H */