4 * AM33xx specific header file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
15 #include <asm/types.h>
16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
18 #include <asm/arch/hardware.h>
20 #define BIT(x) (1 << x)
21 #define CL_BIT(x) (0 << x)
23 /* Timer register bits */
24 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */
25 #define TCLR_AR BIT(1) /* Auto reload */
26 #define TCLR_PRE BIT(5) /* Pre-scaler enable */
27 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
28 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
29 #define TCLR_CE BIT(6) /* compare mode enable */
30 #define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
31 #define TCLR_TCM BIT(8) /* edge detection of input pin*/
32 #define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
33 #define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
34 #define TCLR_CAPTMODE BIT(13) /* capture mode */
35 #define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
37 #define TCFG_RESET BIT(0) /* software reset */
38 #define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
39 #define TCFG_IDLEMOD_SHIFT (2) /* power management */
41 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
42 #define TST_DEVICE 0x0
43 #define EMU_DEVICE 0x1
47 /* cpu-id for AM33XX and TI81XX family */
50 #define DEVICE_ID (CTRL_BASE + 0x0600)
51 #define DEVICE_ID_MASK 0x1FFF
53 /* MPU max frequencies */
54 #define AM335X_ZCZ_300 0x1FEF
55 #define AM335X_ZCZ_600 0x1FAF
56 #define AM335X_ZCZ_720 0x1F2F
57 #define AM335X_ZCZ_800 0x1E2F
58 #define AM335X_ZCZ_1000 0x1C2F
59 #define AM335X_ZCE_300 0x1FDF
60 #define AM335X_ZCE_600 0x1F9F
62 /* This gives the status of the boot mode pins on the evm */
63 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
66 #define PRM_RSTCTRL_RESET 0x01
67 #define PRM_RSTST_WARM_RESET_MASK 0x232
71 * Using the prescaler, the OMAP watchdog could go for many
72 * months before firing. These limits work without scaling,
73 * with the 60 second default assumed by most tools and docs.
75 #define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
76 #define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
77 #define TIMER_MARGIN_MIN 1
79 #define PTV 0 /* prescale */
80 #define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
81 #define WDT_WWPS_PEND_WCLR BIT(0)
82 #define WDT_WWPS_PEND_WLDR BIT(2)
83 #define WDT_WWPS_PEND_WTGR BIT(3)
84 #define WDT_WWPS_PEND_WSPR BIT(4)
86 #define WDT_WCLR_PRE BIT(5)
87 #define WDT_WCLR_PTV_OFF 2
89 #ifndef __KERNEL_STRICT_NAMES
94 /* Encapsulating core pll registers */
96 unsigned int wkclkstctrl; /* offset 0x00 */
97 unsigned int wkctrlclkctrl; /* offset 0x04 */
98 unsigned int wkgpio0clkctrl; /* offset 0x08 */
99 unsigned int wkl4wkclkctrl; /* offset 0x0c */
100 unsigned int timer0clkctrl; /* offset 0x10 */
101 unsigned int resv2[3];
102 unsigned int idlestdpllmpu; /* offset 0x20 */
103 unsigned int resv3[2];
104 unsigned int clkseldpllmpu; /* offset 0x2c */
105 unsigned int resv4[1];
106 unsigned int idlestdpllddr; /* offset 0x34 */
107 unsigned int resv5[2];
108 unsigned int clkseldpllddr; /* offset 0x40 */
109 unsigned int resv6[4];
110 unsigned int clkseldplldisp; /* offset 0x54 */
111 unsigned int resv7[1];
112 unsigned int idlestdpllcore; /* offset 0x5c */
113 unsigned int resv8[2];
114 unsigned int clkseldpllcore; /* offset 0x68 */
115 unsigned int resv9[1];
116 unsigned int idlestdpllper; /* offset 0x70 */
117 unsigned int resv10[2];
118 unsigned int clkdcoldodpllper; /* offset 0x7c */
119 unsigned int divm4dpllcore; /* offset 0x80 */
120 unsigned int divm5dpllcore; /* offset 0x84 */
121 unsigned int clkmoddpllmpu; /* offset 0x88 */
122 unsigned int clkmoddpllper; /* offset 0x8c */
123 unsigned int clkmoddpllcore; /* offset 0x90 */
124 unsigned int clkmoddpllddr; /* offset 0x94 */
125 unsigned int clkmoddplldisp; /* offset 0x98 */
126 unsigned int clkseldpllper; /* offset 0x9c */
127 unsigned int divm2dpllddr; /* offset 0xA0 */
128 unsigned int divm2dplldisp; /* offset 0xA4 */
129 unsigned int divm2dpllmpu; /* offset 0xA8 */
130 unsigned int divm2dpllper; /* offset 0xAC */
131 unsigned int resv11[1];
132 unsigned int wkup_uart0ctrl; /* offset 0xB4 */
133 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
134 unsigned int wkup_adctscctrl; /* offset 0xBC */
136 unsigned int timer1clkctrl; /* offset 0xC4 */
137 unsigned int resv13[4];
138 unsigned int divm6dpllcore; /* offset 0xD8 */
142 * Encapsulating peripheral functional clocks
146 unsigned int l4lsclkstctrl; /* offset 0x00 */
147 unsigned int l3sclkstctrl; /* offset 0x04 */
148 unsigned int l4fwclkstctrl; /* offset 0x08 */
149 unsigned int l3clkstctrl; /* offset 0x0c */
151 unsigned int cpgmac0clkctrl; /* offset 0x14 */
152 unsigned int lcdclkctrl; /* offset 0x18 */
153 unsigned int usb0clkctrl; /* offset 0x1C */
155 unsigned int tptc0clkctrl; /* offset 0x24 */
156 unsigned int emifclkctrl; /* offset 0x28 */
157 unsigned int ocmcramclkctrl; /* offset 0x2c */
158 unsigned int gpmcclkctrl; /* offset 0x30 */
159 unsigned int mcasp0clkctrl; /* offset 0x34 */
160 unsigned int uart5clkctrl; /* offset 0x38 */
161 unsigned int mmc0clkctrl; /* offset 0x3C */
162 unsigned int elmclkctrl; /* offset 0x40 */
163 unsigned int i2c2clkctrl; /* offset 0x44 */
164 unsigned int i2c1clkctrl; /* offset 0x48 */
165 unsigned int spi0clkctrl; /* offset 0x4C */
166 unsigned int spi1clkctrl; /* offset 0x50 */
167 unsigned int resv3[3];
168 unsigned int l4lsclkctrl; /* offset 0x60 */
169 unsigned int l4fwclkctrl; /* offset 0x64 */
170 unsigned int mcasp1clkctrl; /* offset 0x68 */
171 unsigned int uart1clkctrl; /* offset 0x6C */
172 unsigned int uart2clkctrl; /* offset 0x70 */
173 unsigned int uart3clkctrl; /* offset 0x74 */
174 unsigned int uart4clkctrl; /* offset 0x78 */
175 unsigned int timer7clkctrl; /* offset 0x7C */
176 unsigned int timer2clkctrl; /* offset 0x80 */
177 unsigned int timer3clkctrl; /* offset 0x84 */
178 unsigned int timer4clkctrl; /* offset 0x88 */
179 unsigned int resv4[8];
180 unsigned int gpio1clkctrl; /* offset 0xAC */
181 unsigned int gpio2clkctrl; /* offset 0xB0 */
182 unsigned int gpio3clkctrl; /* offset 0xB4 */
184 unsigned int tpccclkctrl; /* offset 0xBC */
185 unsigned int dcan0clkctrl; /* offset 0xC0 */
186 unsigned int dcan1clkctrl; /* offset 0xC4 */
188 unsigned int epwmss1clkctrl; /* offset 0xCC */
189 unsigned int emiffwclkctrl; /* offset 0xD0 */
190 unsigned int epwmss0clkctrl; /* offset 0xD4 */
191 unsigned int epwmss2clkctrl; /* offset 0xD8 */
192 unsigned int l3instrclkctrl; /* offset 0xDC */
193 unsigned int l3clkctrl; /* Offset 0xE0 */
194 unsigned int resv8[2];
195 unsigned int timer5clkctrl; /* offset 0xEC */
196 unsigned int timer6clkctrl; /* offset 0xF0 */
197 unsigned int mmc1clkctrl; /* offset 0xF4 */
198 unsigned int mmc2clkctrl; /* offset 0xF8 */
199 unsigned int resv9[8];
200 unsigned int l4hsclkstctrl; /* offset 0x11C */
201 unsigned int l4hsclkctrl; /* offset 0x120 */
202 unsigned int resv10[8];
203 unsigned int cpswclkstctrl; /* offset 0x144 */
204 unsigned int lcdcclkstctrl; /* offset 0x148 */
207 /* Encapsulating Display pll registers */
210 unsigned int clktimer7clk; /* offset 0x04 */
211 unsigned int clktimer2clk; /* offset 0x08 */
212 unsigned int clktimer3clk; /* offset 0x0C */
213 unsigned int clktimer4clk; /* offset 0x10 */
215 unsigned int clktimer5clk; /* offset 0x18 */
216 unsigned int clktimer6clk; /* offset 0x1C */
217 unsigned int resv3[2];
218 unsigned int clktimer1clk; /* offset 0x28 */
219 unsigned int resv4[2];
220 unsigned int clklcdcpixelclk; /* offset 0x34 */
223 /* Encapsulating core pll registers */
225 unsigned int resv0[136];
226 unsigned int wkl4wkclkctrl; /* offset 0x220 */
227 unsigned int resv1[55];
228 unsigned int wkclkstctrl; /* offset 0x300 */
229 unsigned int resv2[15];
230 unsigned int wkup_i2c0ctrl; /* offset 0x340 */
232 unsigned int wkup_uart0ctrl; /* offset 0x348 */
233 unsigned int resv4[5];
234 unsigned int wkctrlclkctrl; /* offset 0x360 */
236 unsigned int wkgpio0clkctrl; /* offset 0x368 */
238 unsigned int resv6[109];
239 unsigned int clkmoddpllcore; /* offset 0x520 */
240 unsigned int idlestdpllcore; /* offset 0x524 */
242 unsigned int clkseldpllcore; /* offset 0x52C */
243 unsigned int resv7[2];
244 unsigned int divm4dpllcore; /* offset 0x538 */
245 unsigned int divm5dpllcore; /* offset 0x53C */
246 unsigned int divm6dpllcore; /* offset 0x540 */
248 unsigned int resv8[7];
249 unsigned int clkmoddpllmpu; /* offset 0x560 */
250 unsigned int idlestdpllmpu; /* offset 0x564 */
252 unsigned int clkseldpllmpu; /* offset 0x56c */
253 unsigned int divm2dpllmpu; /* offset 0x570 */
255 unsigned int resv10[11];
256 unsigned int clkmoddpllddr; /* offset 0x5A0 */
257 unsigned int idlestdpllddr; /* offset 0x5A4 */
259 unsigned int clkseldpllddr; /* offset 0x5AC */
260 unsigned int divm2dpllddr; /* offset 0x5B0 */
262 unsigned int resv12[11];
263 unsigned int clkmoddpllper; /* offset 0x5E0 */
264 unsigned int idlestdpllper; /* offset 0x5E4 */
266 unsigned int clkseldpllper; /* offset 0x5EC */
267 unsigned int divm2dpllper; /* offset 0x5F0 */
268 unsigned int resv14[8];
269 unsigned int clkdcoldodpllper; /* offset 0x614 */
271 unsigned int resv15[2];
272 unsigned int clkmoddplldisp; /* offset 0x620 */
273 unsigned int resv16[2];
274 unsigned int clkseldplldisp; /* offset 0x62C */
275 unsigned int divm2dplldisp; /* offset 0x630 */
279 * Encapsulating peripheral functional clocks
283 unsigned int l3clkstctrl; /* offset 0x00 */
284 unsigned int resv0[7];
285 unsigned int l3clkctrl; /* Offset 0x20 */
286 unsigned int resv1[7];
287 unsigned int l3instrclkctrl; /* offset 0x40 */
288 unsigned int resv2[3];
289 unsigned int ocmcramclkctrl; /* offset 0x50 */
290 unsigned int resv3[9];
291 unsigned int tpccclkctrl; /* offset 0x78 */
293 unsigned int tptc0clkctrl; /* offset 0x80 */
295 unsigned int resv5[7];
296 unsigned int l4hsclkctrl; /* offset 0x0A0 */
298 unsigned int l4fwclkctrl; /* offset 0x0A8 */
299 unsigned int resv7[85];
300 unsigned int l3sclkstctrl; /* offset 0x200 */
301 unsigned int resv8[7];
302 unsigned int gpmcclkctrl; /* offset 0x220 */
303 unsigned int resv9[5];
304 unsigned int mcasp0clkctrl; /* offset 0x238 */
306 unsigned int mcasp1clkctrl; /* offset 0x240 */
308 unsigned int mmc2clkctrl; /* offset 0x248 */
309 unsigned int resv12[3];
310 unsigned int qspiclkctrl; /* offset 0x258 */
311 unsigned int resv121;
312 unsigned int usb0clkctrl; /* offset 0x260 */
313 unsigned int resv13[103];
314 unsigned int l4lsclkstctrl; /* offset 0x400 */
315 unsigned int resv14[7];
316 unsigned int l4lsclkctrl; /* offset 0x420 */
318 unsigned int dcan0clkctrl; /* offset 0x428 */
320 unsigned int dcan1clkctrl; /* offset 0x430 */
321 unsigned int resv17[13];
322 unsigned int elmclkctrl; /* offset 0x468 */
324 unsigned int resv18[3];
325 unsigned int gpio1clkctrl; /* offset 0x478 */
327 unsigned int gpio2clkctrl; /* offset 0x480 */
329 unsigned int gpio3clkctrl; /* offset 0x488 */
331 unsigned int gpio4clkctrl; /* offset 0x490 */
333 unsigned int gpio5clkctrl; /* offset 0x498 */
334 unsigned int resv21[3];
336 unsigned int i2c1clkctrl; /* offset 0x4A8 */
338 unsigned int i2c2clkctrl; /* offset 0x4B0 */
339 unsigned int resv23[3];
340 unsigned int mmc0clkctrl; /* offset 0x4C0 */
342 unsigned int mmc1clkctrl; /* offset 0x4C8 */
344 unsigned int resv25[13];
345 unsigned int spi0clkctrl; /* offset 0x500 */
347 unsigned int spi1clkctrl; /* offset 0x508 */
348 unsigned int resv27[9];
349 unsigned int timer2clkctrl; /* offset 0x530 */
351 unsigned int timer3clkctrl; /* offset 0x538 */
353 unsigned int timer4clkctrl; /* offset 0x540 */
354 unsigned int resv30[5];
355 unsigned int timer7clkctrl; /* offset 0x558 */
357 unsigned int resv31[9];
358 unsigned int uart1clkctrl; /* offset 0x580 */
360 unsigned int uart2clkctrl; /* offset 0x588 */
362 unsigned int uart3clkctrl; /* offset 0x590 */
364 unsigned int uart4clkctrl; /* offset 0x598 */
366 unsigned int uart5clkctrl; /* offset 0x5A0 */
367 unsigned int resv36[87];
369 unsigned int emifclkstctrl; /* offset 0x700 */
370 unsigned int resv361[7];
371 unsigned int emifclkctrl; /* offset 0x720 */
372 unsigned int resv37[3];
373 unsigned int emiffwclkctrl; /* offset 0x730 */
374 unsigned int resv371;
375 unsigned int otfaemifclkctrl; /* offset 0x738 */
376 unsigned int resv38[57];
377 unsigned int lcdclkctrl; /* offset 0x820 */
378 unsigned int resv39[183];
379 unsigned int cpswclkstctrl; /* offset 0xB00 */
380 unsigned int resv40[7];
381 unsigned int cpgmac0clkctrl; /* offset 0xB20 */
384 struct cm_device_inst {
385 unsigned int cm_clkout1_ctrl;
386 unsigned int cm_dll_ctrl;
391 unsigned int clktimer2clk; /* offset 0x04 */
393 #endif /* CONFIG_AM43XX */
395 /* Control Module RTC registers */
397 unsigned int rtcclkctrl; /* offset 0x0 */
398 unsigned int clkstctrl; /* offset 0x4 */
401 /* Watchdog timer registers */
403 unsigned int resv1[4];
404 unsigned int wdtwdsc; /* offset 0x010 */
405 unsigned int wdtwdst; /* offset 0x014 */
406 unsigned int wdtwisr; /* offset 0x018 */
407 unsigned int wdtwier; /* offset 0x01C */
408 unsigned int wdtwwer; /* offset 0x020 */
409 unsigned int wdtwclr; /* offset 0x024 */
410 unsigned int wdtwcrr; /* offset 0x028 */
411 unsigned int wdtwldr; /* offset 0x02C */
412 unsigned int wdtwtgr; /* offset 0x030 */
413 unsigned int wdtwwps; /* offset 0x034 */
414 unsigned int resv2[3];
415 unsigned int wdtwdly; /* offset 0x044 */
416 unsigned int wdtwspr; /* offset 0x048 */
417 unsigned int resv3[1];
418 unsigned int wdtwqeoi; /* offset 0x050 */
419 unsigned int wdtwqstar; /* offset 0x054 */
420 unsigned int wdtwqsta; /* offset 0x058 */
421 unsigned int wdtwqens; /* offset 0x05C */
422 unsigned int wdtwqenc; /* offset 0x060 */
423 unsigned int resv4[39];
424 unsigned int wdt_unfr; /* offset 0x100 */
427 /* Timer 32 bit registers */
429 unsigned int tidr; /* offset 0x00 */
430 unsigned char res1[12];
431 unsigned int tiocp_cfg; /* offset 0x10 */
432 unsigned char res2[12];
433 unsigned int tier; /* offset 0x20 */
434 unsigned int tistatr; /* offset 0x24 */
435 unsigned int tistat; /* offset 0x28 */
436 unsigned int tisr; /* offset 0x2c */
437 unsigned int tcicr; /* offset 0x30 */
438 unsigned int twer; /* offset 0x34 */
439 unsigned int tclr; /* offset 0x38 */
440 unsigned int tcrr; /* offset 0x3c */
441 unsigned int tldr; /* offset 0x40 */
442 unsigned int ttgr; /* offset 0x44 */
443 unsigned int twpc; /* offset 0x48 */
444 unsigned int tmar; /* offset 0x4c */
445 unsigned int tcar1; /* offset 0x50 */
446 unsigned int tscir; /* offset 0x54 */
447 unsigned int tcar2; /* offset 0x58 */
452 unsigned int resv1[21];
453 unsigned int uartsyscfg; /* offset 0x54 */
454 unsigned int uartsyssts; /* offset 0x58 */
459 unsigned int vtp0ctrlreg;
462 /* Control Status Register */
464 unsigned int resv1[16];
465 unsigned int statusreg; /* ofset 0x40 */
466 unsigned int resv2[51];
467 unsigned int secure_emif_sdram_config; /* offset 0x0110 */
468 unsigned int resv3[319];
469 unsigned int dev_attr;
472 /* AM33XX GPIO registers */
473 #define OMAP_GPIO_REVISION 0x0000
474 #define OMAP_GPIO_SYSCONFIG 0x0010
475 #define OMAP_GPIO_SYSSTATUS 0x0114
476 #define OMAP_GPIO_IRQSTATUS1 0x002c
477 #define OMAP_GPIO_IRQSTATUS2 0x0030
478 #define OMAP_GPIO_CTRL 0x0130
479 #define OMAP_GPIO_OE 0x0134
480 #define OMAP_GPIO_DATAIN 0x0138
481 #define OMAP_GPIO_DATAOUT 0x013c
482 #define OMAP_GPIO_LEVELDETECT0 0x0140
483 #define OMAP_GPIO_LEVELDETECT1 0x0144
484 #define OMAP_GPIO_RISINGDETECT 0x0148
485 #define OMAP_GPIO_FALLINGDETECT 0x014c
486 #define OMAP_GPIO_DEBOUNCE_EN 0x0150
487 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154
488 #define OMAP_GPIO_CLEARDATAOUT 0x0190
489 #define OMAP_GPIO_SETDATAOUT 0x0194
491 /* Control Device Register */
493 /* Control Device Register */
494 #define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
495 #define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
496 #define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
499 unsigned int deviceid; /* offset 0x00 */
500 unsigned int resv1[7];
501 unsigned int usb_ctrl0; /* offset 0x20 */
503 unsigned int usb_ctrl1; /* offset 0x28 */
505 unsigned int macid0l; /* offset 0x30 */
506 unsigned int macid0h; /* offset 0x34 */
507 unsigned int macid1l; /* offset 0x38 */
508 unsigned int macid1h; /* offset 0x3c */
509 unsigned int resv4[4];
510 unsigned int miisel; /* offset 0x50 */
511 unsigned int resv5[7];
512 unsigned int mreqprio_0; /* offset 0x70 */
513 unsigned int mreqprio_1; /* offset 0x74 */
514 unsigned int resv6[97];
515 unsigned int efuse_sma; /* offset 0x1FC */
518 /* Bandwidth Limiter Portion of the L3Fast Configuration Register */
519 #define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
520 #define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
521 #define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
523 struct l3f_cfg_bwlimiter {
525 u32 modena_init0_bw_fractional;
526 u32 modena_init0_bw_integer;
527 u32 modena_init0_watermark_0;
530 /* gmii_sel register defines */
531 #define GMII1_SEL_MII 0x0
532 #define GMII1_SEL_RMII 0x1
533 #define GMII1_SEL_RGMII 0x2
534 #define GMII2_SEL_MII 0x0
535 #define GMII2_SEL_RMII 0x4
536 #define GMII2_SEL_RGMII 0x8
537 #define RGMII1_IDMODE BIT(4)
538 #define RGMII2_IDMODE BIT(5)
539 #define RMII1_IO_CLK_EN BIT(6)
540 #define RMII2_IO_CLK_EN BIT(7)
542 #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
543 #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
544 #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
545 #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
546 #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
551 unsigned int sysconfig;
552 unsigned int clkconfig;
553 unsigned int clkstatus;
555 #define ECAP_CLK_EN BIT(0)
556 #define ECAP_CLK_STOP_REQ BIT(1)
558 struct pwmss_ecap_regs {
565 unsigned int resv1[4];
566 unsigned short ecctl1;
567 unsigned short ecctl2;
570 /* Capture Control register 2 */
571 #define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
572 #define ECTRL2_MDSL_ECAP BIT(9)
573 #define ECTRL2_CTRSTP_FREERUN BIT(4)
574 #define ECTRL2_PLSL_LOW BIT(10)
575 #define ECTRL2_SYNC_EN BIT(5)
577 #endif /* __ASSEMBLY__ */
578 #endif /* __KERNEL_STRICT_NAMES */
580 #endif /* _AM33XX_CPU_H */