4 * AM33xx specific header file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
22 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
23 #include <asm/types.h>
24 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
26 #include <asm/arch/hardware.h>
28 #define BIT(x) (1 << x)
29 #define CL_BIT(x) (0 << x)
31 /* Timer register bits */
32 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */
33 #define TCLR_AR BIT(1) /* Auto reload */
34 #define TCLR_PRE BIT(5) /* Pre-scaler enable */
35 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
36 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
39 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
40 #define TST_DEVICE 0x0
41 #define EMU_DEVICE 0x1
45 /* cpu-id for AM33XX family */
47 #define DEVICE_ID 0x44E10600
49 /* This gives the status of the boot mode pins on the evm */
50 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
55 #define PRM_RSTCTRL 0x44E00F00
57 #define PRM_RSTCTRL_RESET 0x01
59 #ifndef __KERNEL_STRICT_NAMES
61 /* Encapsulating core pll registers */
63 unsigned int wkclkstctrl; /* offset 0x00 */
64 unsigned int wkctrlclkctrl; /* offset 0x04 */
65 unsigned int wkgpio0clkctrl; /* offset 0x08 */
66 unsigned int wkl4wkclkctrl; /* offset 0x0c */
67 unsigned int resv2[4];
68 unsigned int idlestdpllmpu; /* offset 0x20 */
69 unsigned int resv3[2];
70 unsigned int clkseldpllmpu; /* offset 0x2c */
71 unsigned int resv4[1];
72 unsigned int idlestdpllddr; /* offset 0x34 */
73 unsigned int resv5[2];
74 unsigned int clkseldpllddr; /* offset 0x40 */
75 unsigned int resv6[4];
76 unsigned int clkseldplldisp; /* offset 0x54 */
77 unsigned int resv7[1];
78 unsigned int idlestdpllcore; /* offset 0x5c */
79 unsigned int resv8[2];
80 unsigned int clkseldpllcore; /* offset 0x68 */
81 unsigned int resv9[1];
82 unsigned int idlestdpllper; /* offset 0x70 */
83 unsigned int resv10[3];
84 unsigned int divm4dpllcore; /* offset 0x80 */
85 unsigned int divm5dpllcore; /* offset 0x84 */
86 unsigned int clkmoddpllmpu; /* offset 0x88 */
87 unsigned int clkmoddpllper; /* offset 0x8c */
88 unsigned int clkmoddpllcore; /* offset 0x90 */
89 unsigned int clkmoddpllddr; /* offset 0x94 */
90 unsigned int clkmoddplldisp; /* offset 0x98 */
91 unsigned int clkseldpllper; /* offset 0x9c */
92 unsigned int divm2dpllddr; /* offset 0xA0 */
93 unsigned int divm2dplldisp; /* offset 0xA4 */
94 unsigned int divm2dpllmpu; /* offset 0xA8 */
95 unsigned int divm2dpllper; /* offset 0xAC */
96 unsigned int resv11[1];
97 unsigned int wkup_uart0ctrl; /* offset 0xB4 */
98 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
99 unsigned int resv12[7];
100 unsigned int divm6dpllcore; /* offset 0xD8 */
104 * Encapsulating peripheral functional clocks
108 unsigned int l4lsclkstctrl; /* offset 0x00 */
109 unsigned int l3sclkstctrl; /* offset 0x04 */
110 unsigned int l4fwclkstctrl; /* offset 0x08 */
111 unsigned int l3clkstctrl; /* offset 0x0c */
113 unsigned int cpgmac0clkctrl; /* offset 0x14 */
114 unsigned int lcdclkctrl; /* offset 0x18 */
115 unsigned int usb0clkctrl; /* offset 0x1C */
117 unsigned int tptc0clkctrl; /* offset 0x24 */
118 unsigned int emifclkctrl; /* offset 0x28 */
119 unsigned int ocmcramclkctrl; /* offset 0x2c */
120 unsigned int gpmcclkctrl; /* offset 0x30 */
121 unsigned int mcasp0clkctrl; /* offset 0x34 */
122 unsigned int uart5clkctrl; /* offset 0x38 */
123 unsigned int mmc0clkctrl; /* offset 0x3C */
124 unsigned int elmclkctrl; /* offset 0x40 */
125 unsigned int i2c2clkctrl; /* offset 0x44 */
126 unsigned int i2c1clkctrl; /* offset 0x48 */
127 unsigned int spi0clkctrl; /* offset 0x4C */
128 unsigned int spi1clkctrl; /* offset 0x50 */
129 unsigned int resv3[3];
130 unsigned int l4lsclkctrl; /* offset 0x60 */
131 unsigned int l4fwclkctrl; /* offset 0x64 */
132 unsigned int mcasp1clkctrl; /* offset 0x68 */
133 unsigned int uart1clkctrl; /* offset 0x6C */
134 unsigned int uart2clkctrl; /* offset 0x70 */
135 unsigned int uart3clkctrl; /* offset 0x74 */
136 unsigned int uart4clkctrl; /* offset 0x78 */
137 unsigned int timer7clkctrl; /* offset 0x7C */
138 unsigned int timer2clkctrl; /* offset 0x80 */
139 unsigned int timer3clkctrl; /* offset 0x84 */
140 unsigned int timer4clkctrl; /* offset 0x88 */
141 unsigned int resv4[8];
142 unsigned int gpio1clkctrl; /* offset 0xAC */
143 unsigned int gpio2clkctrl; /* offset 0xB0 */
144 unsigned int gpio3clkctrl; /* offset 0xB4 */
146 unsigned int tpccclkctrl; /* offset 0xBC */
147 unsigned int dcan0clkctrl; /* offset 0xC0 */
148 unsigned int dcan1clkctrl; /* offset 0xC4 */
149 unsigned int resv6[2];
150 unsigned int emiffwclkctrl; /* offset 0xD0 */
151 unsigned int resv7[2];
152 unsigned int l3instrclkctrl; /* offset 0xDC */
153 unsigned int l3clkctrl; /* Offset 0xE0 */
154 unsigned int resv8[4];
155 unsigned int mmc1clkctrl; /* offset 0xF4 */
156 unsigned int mmc2clkctrl; /* offset 0xF8 */
157 unsigned int resv9[8];
158 unsigned int l4hsclkstctrl; /* offset 0x11C */
159 unsigned int l4hsclkctrl; /* offset 0x120 */
160 unsigned int resv10[8];
161 unsigned int cpswclkstctrl; /* offset 0x144 */
164 /* Encapsulating Display pll registers */
166 unsigned int resv1[2];
167 unsigned int clktimer2clk; /* offset 0x08 */
170 /* Watchdog timer registers */
172 unsigned int resv1[4];
173 unsigned int wdtwdsc; /* offset 0x010 */
174 unsigned int wdtwdst; /* offset 0x014 */
175 unsigned int wdtwisr; /* offset 0x018 */
176 unsigned int wdtwier; /* offset 0x01C */
177 unsigned int wdtwwer; /* offset 0x020 */
178 unsigned int wdtwclr; /* offset 0x024 */
179 unsigned int wdtwcrr; /* offset 0x028 */
180 unsigned int wdtwldr; /* offset 0x02C */
181 unsigned int wdtwtgr; /* offset 0x030 */
182 unsigned int wdtwwps; /* offset 0x034 */
183 unsigned int resv2[3];
184 unsigned int wdtwdly; /* offset 0x044 */
185 unsigned int wdtwspr; /* offset 0x048 */
186 unsigned int resv3[1];
187 unsigned int wdtwqeoi; /* offset 0x050 */
188 unsigned int wdtwqstar; /* offset 0x054 */
189 unsigned int wdtwqsta; /* offset 0x058 */
190 unsigned int wdtwqens; /* offset 0x05C */
191 unsigned int wdtwqenc; /* offset 0x060 */
192 unsigned int resv4[39];
193 unsigned int wdt_unfr; /* offset 0x100 */
196 /* Timer 32 bit registers */
198 unsigned int tidr; /* offset 0x00 */
199 unsigned char res1[12];
200 unsigned int tiocp_cfg; /* offset 0x10 */
201 unsigned char res2[12];
202 unsigned int tier; /* offset 0x20 */
203 unsigned int tistatr; /* offset 0x24 */
204 unsigned int tistat; /* offset 0x28 */
205 unsigned int tisr; /* offset 0x2c */
206 unsigned int tcicr; /* offset 0x30 */
207 unsigned int twer; /* offset 0x34 */
208 unsigned int tclr; /* offset 0x38 */
209 unsigned int tcrr; /* offset 0x3c */
210 unsigned int tldr; /* offset 0x40 */
211 unsigned int ttgr; /* offset 0x44 */
212 unsigned int twpc; /* offset 0x48 */
213 unsigned int tmar; /* offset 0x4c */
214 unsigned int tcar1; /* offset 0x50 */
215 unsigned int tscir; /* offset 0x54 */
216 unsigned int tcar2; /* offset 0x58 */
221 unsigned int resv1[21];
222 unsigned int uartsyscfg; /* offset 0x54 */
223 unsigned int uartsyssts; /* offset 0x58 */
228 unsigned int vtp0ctrlreg;
231 /* Control Status Register */
233 unsigned int resv1[16];
234 unsigned int statusreg; /* ofset 0x40 */
236 #endif /* __ASSEMBLY__ */
237 #endif /* __KERNEL_STRICT_NAMES */
239 #endif /* _AM33XX_CPU_H */