3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/arch/crm_regs.h>
34 #ifdef CONFIG_FSL_ESDHC
35 #include <fsl_esdhc.h>
38 char *get_reset_cause(void)
41 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
43 cause = readl(&src_regs->srsr);
44 writel(cause, &src_regs->srsr);
63 return "unknown reset";
67 #if defined(CONFIG_DISPLAY_CPUINFO)
69 static const char *get_imx_type(u32 imxtype)
73 return "6Q"; /* Quad-core version of the mx6 */
75 return "6DS"; /* Dual/Solo version of the mx6 */
77 return "6SL"; /* Solo-Lite version of the mx6 */
87 int print_cpuinfo(void)
91 cpurev = get_cpu_rev();
93 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
94 get_imx_type((cpurev & 0xFF000) >> 12),
95 (cpurev & 0x000F0) >> 4,
96 (cpurev & 0x0000F) >> 0,
97 mxc_get_clock(MXC_ARM_CLK) / 1000000);
98 printf("Reset cause: %s\n", get_reset_cause());
103 int cpu_eth_init(bd_t *bis)
107 #if defined(CONFIG_FEC_MXC)
108 rc = fecmxc_initialize(bis);
114 #ifdef CONFIG_FSL_ESDHC
116 * Initializes on-chip MMC controllers.
117 * to override, implement board_mmc_init()
119 int cpu_mmc_init(bd_t *bis)
121 return fsl_esdhc_mmc_init(bis);
125 void reset_cpu(ulong addr)
127 __raw_writew(4, WDOG1_BASE_ADDR);
130 u32 get_ahb_clk(void)
132 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
135 reg = __raw_readl(&imx_ccm->cbcdr);
136 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
137 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
139 return get_periph_clk() / (ahb_podf + 1);