3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/crm_regs.h>
19 #include <ipu_pixfmt.h>
23 #ifdef CONFIG_FSL_ESDHC
24 #include <fsl_esdhc.h>
27 static u32 reset_cause = -1;
29 static char *get_reset_cause(void)
32 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
34 cause = readl(&src_regs->srsr);
35 writel(cause, &src_regs->srsr);
55 return "unknown reset";
59 u32 get_imx_reset_cause(void)
64 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
65 #if defined(CONFIG_MX53)
66 #define MEMCTL_BASE ESDCTL_BASE_ADDR
68 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
70 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
71 static const unsigned char bank_lookup[] = {3, 2};
73 /* these MMDC registers are common to the IMX53 and IMX6 */
74 struct esd_mmdc_regs {
84 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
85 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
86 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
87 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
88 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
91 * imx_ddr_size - return size in bytes of DRAM according MMDC config
92 * The MMDC MDCTL register holds the number of bits for row, col, and data
93 * width and the MMDC MDMISC register holds the number of banks. Combine
94 * all these bits to determine the meme size the MMDC has been configured for
96 unsigned imx_ddr_size(void)
98 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
99 unsigned ctl = readl(&mem->ctl);
100 unsigned misc = readl(&mem->misc);
101 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
103 bits += ESD_MMDC_CTL_GET_ROW(ctl);
104 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
105 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
106 bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
107 bits += ESD_MMDC_CTL_GET_CS1(ctl);
109 /* The MX6 can do only 3840 MiB of DRAM */
117 #if defined(CONFIG_DISPLAY_CPUINFO)
119 const char *get_imx_type(u32 imxtype)
123 return "6Q"; /* Quad-core version of the mx6 */
125 return "6D"; /* Dual-core version of the mx6 */
127 return "6DL"; /* Dual Lite version of the mx6 */
128 case MXC_CPU_MX6SOLO:
129 return "6SOLO"; /* Solo version of the mx6 */
131 return "6SL"; /* Solo-Lite version of the mx6 */
133 return "6SX"; /* SoloX version of the mx6 */
143 int print_cpuinfo(void)
147 #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
148 struct udevice *thermal_dev;
152 cpurev = get_cpu_rev();
154 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
155 get_imx_type((cpurev & 0xFF000) >> 12),
156 (cpurev & 0x000F0) >> 4,
157 (cpurev & 0x0000F) >> 0,
158 mxc_get_clock(MXC_ARM_CLK) / 1000000);
160 #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
161 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
163 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
166 printf("CPU: Temperature %d C\n", cpu_tmp);
168 printf("CPU: Temperature: invalid sensor data\n");
170 printf("CPU: Temperature: Can't find sensor device\n");
174 printf("Reset cause: %s\n", get_reset_cause());
179 int cpu_eth_init(bd_t *bis)
183 #if defined(CONFIG_FEC_MXC)
184 rc = fecmxc_initialize(bis);
190 #ifdef CONFIG_FSL_ESDHC
192 * Initializes on-chip MMC controllers.
193 * to override, implement board_mmc_init()
195 int cpu_mmc_init(bd_t *bis)
197 return fsl_esdhc_mmc_init(bis);
201 u32 get_ahb_clk(void)
203 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
206 reg = __raw_readl(&imx_ccm->cbcdr);
207 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
208 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
210 return get_periph_clk() / (ahb_podf + 1);
213 void arch_preboot_os(void)
215 #if defined(CONFIG_CMD_SATA)
217 #if defined(CONFIG_MX6)
218 disable_sata_clock();
221 #if defined(CONFIG_VIDEO_IPUV3)
222 /* disable video before launching O/S */
227 void set_chipselect_size(int const cs_size)
230 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
231 reg = readl(&iomuxc_regs->gpr[1]);
235 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
238 case CS0_64M_CS1_64M:
239 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
242 case CS0_64M_CS1_32M_CS2_32M:
243 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
246 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
247 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
251 printf("Unknown chip select size: %d\n", cs_size);
255 writel(reg, &iomuxc_regs->gpr[1]);