2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
12 #ifndef CONFIG_SYS_DCACHE_OFF
13 void enable_caches(void)
15 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
16 enum dcache_option option = DCACHE_WRITETHROUGH;
18 enum dcache_option option = DCACHE_WRITEBACK;
20 /* Avoid random hang when download by usb */
21 invalidate_dcache_all();
23 /* Enable D-cache. I-cache is already enabled in start.S */
26 /* Enable caching on OCRAM and ROM */
27 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
30 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
36 #ifndef CONFIG_SYS_L2CACHE_OFF
37 #ifdef CONFIG_SYS_L2_PL310
38 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
39 void v7_outer_cache_enable(void)
41 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
46 * Must disable the L2 before changing the latency parameters
47 * and auxiliary control register.
49 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
52 * Set bit 22 in the auxiliary control register. If this bit
53 * is cleared, PL310 treats Normal Shared Non-cacheable
54 * accesses as Cacheable no-allocate.
56 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
58 #if defined CONFIG_MX6SL
59 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
60 val = readl(&iomux->gpr[11]);
61 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
62 /* L2 cache configured as OCRAM, reset it */
63 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
64 writel(val, &iomux->gpr[11]);
68 writel(0x132, &pl310->pl310_tag_latency_ctrl);
69 writel(0x132, &pl310->pl310_data_latency_ctrl);
71 val = readl(&pl310->pl310_prefetch_ctrl);
73 /* Turn on the L2 I/D prefetch */
77 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
78 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
79 * But according to ARM PL310 errata: 752271
80 * ID: 752271: Double linefill feature can cause data corruption
81 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
82 * Workaround: The only workaround to this erratum is to disable the
83 * double linefill feature. This is the default behavior.
89 writel(val, &pl310->pl310_prefetch_ctrl);
91 val = readl(&pl310->pl310_power_ctrl);
92 val |= L2X0_DYNAMIC_CLK_GATING_EN;
93 val |= L2X0_STNDBY_MODE_EN;
94 writel(val, &pl310->pl310_power_ctrl);
96 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
99 void v7_outer_cache_disable(void)
101 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
103 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
105 #endif /* !CONFIG_SYS_L2_PL310 */
106 #endif /* !CONFIG_SYS_L2CACHE_OFF */