2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/imx-common/sys_proto.h>
13 #ifndef CONFIG_SYS_DCACHE_OFF
14 void enable_caches(void)
16 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
17 enum dcache_option option = DCACHE_WRITETHROUGH;
19 enum dcache_option option = DCACHE_WRITEBACK;
21 /* Avoid random hang when download by usb */
22 invalidate_dcache_all();
24 /* Enable D-cache. I-cache is already enabled in start.S */
27 /* Enable caching on OCRAM and ROM */
28 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
31 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
37 #ifndef CONFIG_SYS_L2CACHE_OFF
38 #ifdef CONFIG_SYS_L2_PL310
39 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
40 void v7_outer_cache_enable(void)
42 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
43 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
48 * Must disable the L2 before changing the latency parameters
49 * and auxiliary control register.
51 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
54 * Set bit 22 in the auxiliary control register. If this bit
55 * is cleared, PL310 treats Normal Shared Non-cacheable
56 * accesses as Cacheable no-allocate.
58 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
60 if (is_mx6sl() || is_mx6sll()) {
61 val = readl(&iomux->gpr[11]);
62 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
63 /* L2 cache configured as OCRAM, reset it */
64 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
65 writel(val, &iomux->gpr[11]);
69 writel(0x132, &pl310->pl310_tag_latency_ctrl);
70 writel(0x132, &pl310->pl310_data_latency_ctrl);
72 val = readl(&pl310->pl310_prefetch_ctrl);
74 /* Turn on the L2 I/D prefetch */
78 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
79 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
80 * But according to ARM PL310 errata: 752271
81 * ID: 752271: Double linefill feature can cause data corruption
82 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
83 * Workaround: The only workaround to this erratum is to disable the
84 * double linefill feature. This is the default behavior.
90 writel(val, &pl310->pl310_prefetch_ctrl);
92 val = readl(&pl310->pl310_power_ctrl);
93 val |= L2X0_DYNAMIC_CLK_GATING_EN;
94 val |= L2X0_STNDBY_MODE_EN;
95 writel(val, &pl310->pl310_power_ctrl);
97 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
100 void v7_outer_cache_disable(void)
102 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
104 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
106 #endif /* !CONFIG_SYS_L2_PL310 */
107 #endif /* !CONFIG_SYS_L2CACHE_OFF */