arch/arm/dts/zynqmp.dtsi

   1 /*
   2  * dts file for Xilinx ZynqMP
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 / {
  12         compatible = "xlnx,zynqmp";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@0 {
  21                         compatible = "arm,cortex-a53", "arm,armv8";
  22                         device_type = "cpu";
  23                         enable-method = "psci";
  24                         operating-points-v2 = <&cpu_opp_table>;
  25                         reg = <0x0>;
  26                         cpu-idle-states = <&CPU_SLEEP_0>;
  27                 };
  28
  29                 cpu1: cpu@1 {
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         device_type = "cpu";
  32                         enable-method = "psci";
  33                         reg = <0x1>;
  34                         operating-points-v2 = <&cpu_opp_table>;
  35                         cpu-idle-states = <&CPU_SLEEP_0>;
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         device_type = "cpu";
  41                         enable-method = "psci";
  42                         reg = <0x2>;
  43                         operating-points-v2 = <&cpu_opp_table>;
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                 };
  46
  47                 cpu3: cpu@3 {
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         device_type = "cpu";
  50                         enable-method = "psci";
  51                         reg = <0x3>;
  52                         operating-points-v2 = <&cpu_opp_table>;
  53                         cpu-idle-states = <&CPU_SLEEP_0>;
  54                 };
  55
  56                 idle-states {
  57                         entry-method = "arm,psci";
  58
  59                         CPU_SLEEP_0: cpu-sleep-0 {
  60                                 compatible = "arm,idle-state";
  61                                 arm,psci-suspend-param = <0x40000000>;
  62                                 local-timer-stop;
  63                                 entry-latency-us = <300>;
  64                                 exit-latency-us = <600>;
  65                                 min-residency-us = <800000>;
  66                         };
  67                 };
  68         };
  69
  70         cpu_opp_table: cpu_opp_table {
  71                 compatible = "operating-points-v2";
  72                 opp-shared;
  73                 opp00 {
  74                         opp-hz = /bits/ 64 <1199999988>;
  75                         opp-microvolt = <1000000>;
  76                         clock-latency-ns = <500000>;
  77                 };
  78                 opp01 {
  79                         opp-hz = /bits/ 64 <599999994>;
  80                         opp-microvolt = <1000000>;
  81                         clock-latency-ns = <500000>;
  82                 };
  83                 opp02 {
  84                         opp-hz = /bits/ 64 <399999996>;
  85                         opp-microvolt = <1000000>;
  86                         clock-latency-ns = <500000>;
  87                 };
  88                 opp03 {
  89                         opp-hz = /bits/ 64 <299999997>;
  90                         opp-microvolt = <1000000>;
  91                         clock-latency-ns = <500000>;
  92                 };
  93         };
  94
  95         dcc: dcc {
  96                 compatible = "arm,dcc";
  97                 status = "disabled";
  98                 u-boot,dm-pre-reloc;
  99         };
 100
 101         power-domains {
 102                 compatible = "xlnx,zynqmp-genpd";
 103
 104                 pd_usb0: pd-usb0 {
 105                         #power-domain-cells = <0x0>;
 106                         pd-id = <0x16>;
 107                 };
 108
 109                 pd_usb1: pd-usb1 {
 110                         #power-domain-cells = <0x0>;
 111                         pd-id = <0x17>;
 112                 };
 113
 114                 pd_sata: pd-sata {
 115                         #power-domain-cells = <0x0>;
 116                         pd-id = <0x1c>;
 117                 };
 118
 119                 pd_spi0: pd-spi0 {
 120                         #power-domain-cells = <0x0>;
 121                         pd-id = <0x23>;
 122                 };
 123
 124                 pd_spi1: pd-spi1 {
 125                         #power-domain-cells = <0x0>;
 126                         pd-id = <0x24>;
 127                 };
 128
 129                 pd_uart0: pd-uart0 {
 130                         #power-domain-cells = <0x0>;
 131                         pd-id = <0x21>;
 132                 };
 133
 134                 pd_uart1: pd-uart1 {
 135                         #power-domain-cells = <0x0>;
 136                         pd-id = <0x22>;
 137                 };
 138
 139                 pd_eth0: pd-eth0 {
 140                         #power-domain-cells = <0x0>;
 141                         pd-id = <0x1d>;
 142                 };
 143
 144                 pd_eth1: pd-eth1 {
 145                         #power-domain-cells = <0x0>;
 146                         pd-id = <0x1e>;
 147                 };
 148
 149                 pd_eth2: pd-eth2 {
 150                         #power-domain-cells = <0x0>;
 151                         pd-id = <0x1f>;
 152                 };
 153
 154                 pd_eth3: pd-eth3 {
 155                         #power-domain-cells = <0x0>;
 156                         pd-id = <0x20>;
 157                 };
 158
 159                 pd_i2c0: pd-i2c0 {
 160                         #power-domain-cells = <0x0>;
 161                         pd-id = <0x25>;
 162                 };
 163
 164                 pd_i2c1: pd-i2c1 {
 165                         #power-domain-cells = <0x0>;
 166                         pd-id = <0x26>;
 167                 };
 168
 169                 pd_dp: pd-dp {
 170                         /* fixme: what to attach to */
 171                         #power-domain-cells = <0x0>;
 172                         pd-id = <0x29>;
 173                 };
 174
 175                 pd_gdma: pd-gdma {
 176                         #power-domain-cells = <0x0>;
 177                         pd-id = <0x2a>;
 178                 };
 179
 180                 pd_adma: pd-adma {
 181                         #power-domain-cells = <0x0>;
 182                         pd-id = <0x2b>;
 183                 };
 184
 185                 pd_ttc0: pd-ttc0 {
 186                         #power-domain-cells = <0x0>;
 187                         pd-id = <0x18>;
 188                 };
 189
 190                 pd_ttc1: pd-ttc1 {
 191                         #power-domain-cells = <0x0>;
 192                         pd-id = <0x19>;
 193                 };
 194
 195                 pd_ttc2: pd-ttc2 {
 196                         #power-domain-cells = <0x0>;
 197                         pd-id = <0x1a>;
 198                 };
 199
 200                 pd_ttc3: pd-ttc3 {
 201                         #power-domain-cells = <0x0>;
 202                         pd-id = <0x1b>;
 203                 };
 204
 205                 pd_sd0: pd-sd0 {
 206                         #power-domain-cells = <0x0>;
 207                         pd-id = <0x27>;
 208                 };
 209
 210                 pd_sd1: pd-sd1 {
 211                         #power-domain-cells = <0x0>;
 212                         pd-id = <0x28>;
 213                 };
 214
 215                 pd_nand: pd-nand {
 216                         #power-domain-cells = <0x0>;
 217                         pd-id = <0x2c>;
 218                 };
 219
 220                 pd_qspi: pd-qspi {
 221                         #power-domain-cells = <0x0>;
 222                         pd-id = <0x2d>;
 223                 };
 224
 225                 pd_gpio: pd-gpio {
 226                         #power-domain-cells = <0x0>;
 227                         pd-id = <0x2e>;
 228                 };
 229
 230                 pd_can0: pd-can0 {
 231                         #power-domain-cells = <0x0>;
 232                         pd-id = <0x2f>;
 233                 };
 234
 235                 pd_can1: pd-can1 {
 236                         #power-domain-cells = <0x0>;
 237                         pd-id = <0x30>;
 238                 };
 239
 240                 pd_pcie: pd-pcie {
 241                         #power-domain-cells = <0x0>;
 242                         pd-id = <0x3b>;
 243                 };
 244
 245                 pd_gpu: pd-gpu {
 246                         #power-domain-cells = <0x0>;
 247                         pd-id = <0x3a 0x14 0x15>;
 248                 };
 249         };
 250
 251         pmu {
 252                 compatible = "arm,armv8-pmuv3";
 253                 interrupt-parent = <&gic>;
 254                 interrupts = <0 143 4>,
 255                              <0 144 4>,
 256                              <0 145 4>,
 257                              <0 146 4>;
 258         };
 259
 260         psci {
 261                 compatible = "arm,psci-0.2";
 262                 method = "smc";
 263         };
 264
 265         firmware {
 266                 compatible = "xlnx,zynqmp-pm";
 267                 method = "smc";
 268         };
 269
 270         timer {
 271                 compatible = "arm,armv8-timer";
 272                 interrupt-parent = <&gic>;
 273                 interrupts = <1 13 0xf01>,
 274                              <1 14 0xf01>,
 275                              <1 11 0xf01>,
 276                              <1 10 0xf01>;
 277         };
 278
 279         edac {
 280                 compatible = "arm,cortex-a53-edac";
 281         };
 282
 283         pcap {
 284                 compatible = "xlnx,zynqmp-pcap-fpga";
 285         };
 286
 287         amba_apu: amba_apu@0 {
 288                 compatible = "simple-bus";
 289                 #address-cells = <2>;
 290                 #size-cells = <1>;
 291                 ranges = <0 0 0 0 0xffffffff>;
 292
 293                 gic: interrupt-controller@f9010000 {
 294                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
 295                         #interrupt-cells = <3>;
 296                         reg = <0x0 0xf9010000 0x10000>,
 297                               <0x0 0xf9020000 0x20000>,
 298                               <0x0 0xf9040000 0x20000>,
 299                               <0x0 0xf9060000 0x20000>;
 300                         interrupt-controller;
 301                         interrupt-parent = <&gic>;
 302                         interrupts = <1 9 0xf04>;
 303                 };
 304         };
 305
 306         amba: amba {
 307                 compatible = "simple-bus";
 308                 u-boot,dm-pre-reloc;
 309                 #address-cells = <2>;
 310                 #size-cells = <2>;
 311                 ranges;
 312
 313                 can0: can@ff060000 {
 314                         compatible = "xlnx,zynq-can-1.0";
 315                         status = "disabled";
 316                         clock-names = "can_clk", "pclk";
 317                         reg = <0x0 0xff060000 0x0 0x1000>;
 318                         interrupts = <0 23 4>;
 319                         interrupt-parent = <&gic>;
 320                         tx-fifo-depth = <0x40>;
 321                         rx-fifo-depth = <0x40>;
 322                         power-domains = <&pd_can0>;
 323                 };
 324
 325                 can1: can@ff070000 {
 326                         compatible = "xlnx,zynq-can-1.0";
 327                         status = "disabled";
 328                         clock-names = "can_clk", "pclk";
 329                         reg = <0x0 0xff070000 0x0 0x1000>;
 330                         interrupts = <0 24 4>;
 331                         interrupt-parent = <&gic>;
 332                         tx-fifo-depth = <0x40>;
 333                         rx-fifo-depth = <0x40>;
 334                         power-domains = <&pd_can1>;
 335                 };
 336
 337                 cci: cci@fd6e0000 {
 338                         compatible = "arm,cci-400";
 339                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 340                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 341                         #address-cells = <1>;
 342                         #size-cells = <1>;
 343
 344                         pmu@9000 {
 345                                 compatible = "arm,cci-400-pmu,r1";
 346                                 reg = <0x9000 0x5000>;
 347                                 interrupt-parent = <&gic>;
 348                                 interrupts = <0 123 4>,
 349                                              <0 123 4>,
 350                                              <0 123 4>,
 351                                              <0 123 4>,
 352                                              <0 123 4>;
 353                         };
 354                 };
 355
 356                 /* GDMA */
 357                 fpd_dma_chan1: dma@fd500000 {
 358                         status = "disabled";
 359                         compatible = "xlnx,zynqmp-dma-1.0";
 360                         reg = <0x0 0xfd500000 0x0 0x1000>;
 361                         interrupt-parent = <&gic>;
 362                         interrupts = <0 124 4>;
 363                         clock-names = "clk_main", "clk_apb";
 364                         xlnx,bus-width = <128>;
 365                         #stream-id-cells = <1>;
 366                         iommus = <&smmu 0x14e8>;
 367                         power-domains = <&pd_gdma>;
 368                 };
 369
 370                 fpd_dma_chan2: dma@fd510000 {
 371                         status = "disabled";
 372                         compatible = "xlnx,zynqmp-dma-1.0";
 373                         reg = <0x0 0xfd510000 0x0 0x1000>;
 374                         interrupt-parent = <&gic>;
 375                         interrupts = <0 125 4>;
 376                         clock-names = "clk_main", "clk_apb";
 377                         xlnx,bus-width = <128>;
 378                         #stream-id-cells = <1>;
 379                         iommus = <&smmu 0x14e9>;
 380                         power-domains = <&pd_gdma>;
 381                 };
 382
 383                 fpd_dma_chan3: dma@fd520000 {
 384                         status = "disabled";
 385                         compatible = "xlnx,zynqmp-dma-1.0";
 386                         reg = <0x0 0xfd520000 0x0 0x1000>;
 387                         interrupt-parent = <&gic>;
 388                         interrupts = <0 126 4>;
 389                         clock-names = "clk_main", "clk_apb";
 390                         xlnx,bus-width = <128>;
 391                         #stream-id-cells = <1>;
 392                         iommus = <&smmu 0x14ea>;
 393                         power-domains = <&pd_gdma>;
 394                 };
 395
 396                 fpd_dma_chan4: dma@fd530000 {
 397                         status = "disabled";
 398                         compatible = "xlnx,zynqmp-dma-1.0";
 399                         reg = <0x0 0xfd530000 0x0 0x1000>;
 400                         interrupt-parent = <&gic>;
 401                         interrupts = <0 127 4>;
 402                         clock-names = "clk_main", "clk_apb";
 403                         xlnx,bus-width = <128>;
 404                         #stream-id-cells = <1>;
 405                         iommus = <&smmu 0x14eb>;
 406                         power-domains = <&pd_gdma>;
 407                 };
 408
 409                 fpd_dma_chan5: dma@fd540000 {
 410                         status = "disabled";
 411                         compatible = "xlnx,zynqmp-dma-1.0";
 412                         reg = <0x0 0xfd540000 0x0 0x1000>;
 413                         interrupt-parent = <&gic>;
 414                         interrupts = <0 128 4>;
 415                         clock-names = "clk_main", "clk_apb";
 416                         xlnx,bus-width = <128>;
 417                         #stream-id-cells = <1>;
 418                         iommus = <&smmu 0x14ec>;
 419                         power-domains = <&pd_gdma>;
 420                 };
 421
 422                 fpd_dma_chan6: dma@fd550000 {
 423                         status = "disabled";
 424                         compatible = "xlnx,zynqmp-dma-1.0";
 425                         reg = <0x0 0xfd550000 0x0 0x1000>;
 426                         interrupt-parent = <&gic>;
 427                         interrupts = <0 129 4>;
 428                         clock-names = "clk_main", "clk_apb";
 429                         xlnx,bus-width = <128>;
 430                         #stream-id-cells = <1>;
 431                         iommus = <&smmu 0x14ed>;
 432                         power-domains = <&pd_gdma>;
 433                 };
 434
 435                 fpd_dma_chan7: dma@fd560000 {
 436                         status = "disabled";
 437                         compatible = "xlnx,zynqmp-dma-1.0";
 438                         reg = <0x0 0xfd560000 0x0 0x1000>;
 439                         interrupt-parent = <&gic>;
 440                         interrupts = <0 130 4>;
 441                         clock-names = "clk_main", "clk_apb";
 442                         xlnx,bus-width = <128>;
 443                         #stream-id-cells = <1>;
 444                         iommus = <&smmu 0x14ee>;
 445                         power-domains = <&pd_gdma>;
 446                 };
 447
 448                 fpd_dma_chan8: dma@fd570000 {
 449                         status = "disabled";
 450                         compatible = "xlnx,zynqmp-dma-1.0";
 451                         reg = <0x0 0xfd570000 0x0 0x1000>;
 452                         interrupt-parent = <&gic>;
 453                         interrupts = <0 131 4>;
 454                         clock-names = "clk_main", "clk_apb";
 455                         xlnx,bus-width = <128>;
 456                         #stream-id-cells = <1>;
 457                         iommus = <&smmu 0x14ef>;
 458                         power-domains = <&pd_gdma>;
 459                 };
 460
 461                 gpu: gpu@fd4b0000 {
 462                         status = "disabled";
 463                         compatible = "arm,mali-400", "arm,mali-utgard";
 464                         reg = <0x0 0xfd4b0000 0x0 0x30000>;
 465                         interrupt-parent = <&gic>;
 466                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 467                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 468                         power-domains = <&pd_gpu>;
 469                 };
 470
 471                 /* LPDDMA default allows only secured access. inorder to enable
 472                  * These dma channels, Users should ensure that these dma
 473                  * Channels are allowed for non secure access.
 474                  */
 475                 lpd_dma_chan1: dma@ffa80000 {
 476                         status = "disabled";
 477                         compatible = "xlnx,zynqmp-dma-1.0";
 478                         clock-names = "clk_main", "clk_apb";
 479                         reg = <0x0 0xffa80000 0x0 0x1000>;
 480                         interrupt-parent = <&gic>;
 481                         interrupts = <0 77 4>;
 482                         xlnx,bus-width = <64>;
 483                         #stream-id-cells = <1>;
 484                         iommus = <&smmu 0x868>;
 485                         power-domains = <&pd_adma>;
 486                 };
 487
 488                 lpd_dma_chan2: dma@ffa90000 {
 489                         status = "disabled";
 490                         compatible = "xlnx,zynqmp-dma-1.0";
 491                         clock-names = "clk_main", "clk_apb";
 492                         reg = <0x0 0xffa90000 0x0 0x1000>;
 493                         interrupt-parent = <&gic>;
 494                         interrupts = <0 78 4>;
 495                         xlnx,bus-width = <64>;
 496                         #stream-id-cells = <1>;
 497                         iommus = <&smmu 0x869>;
 498                         power-domains = <&pd_adma>;
 499                 };
 500
 501                 lpd_dma_chan3: dma@ffaa0000 {
 502                         status = "disabled";
 503                         compatible = "xlnx,zynqmp-dma-1.0";
 504                         clock-names = "clk_main", "clk_apb";
 505                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 506                         interrupt-parent = <&gic>;
 507                         interrupts = <0 79 4>;
 508                         xlnx,bus-width = <64>;
 509                         #stream-id-cells = <1>;
 510                         iommus = <&smmu 0x86a>;
 511                         power-domains = <&pd_adma>;
 512                 };
 513
 514                 lpd_dma_chan4: dma@ffab0000 {
 515                         status = "disabled";
 516                         compatible = "xlnx,zynqmp-dma-1.0";
 517                         clock-names = "clk_main", "clk_apb";
 518                         reg = <0x0 0xffab0000 0x0 0x1000>;
 519                         interrupt-parent = <&gic>;
 520                         interrupts = <0 80 4>;
 521                         xlnx,bus-width = <64>;
 522                         #stream-id-cells = <1>;
 523                         iommus = <&smmu 0x86b>;
 524                         power-domains = <&pd_adma>;
 525                 };
 526
 527                 lpd_dma_chan5: dma@ffac0000 {
 528                         status = "disabled";
 529                         compatible = "xlnx,zynqmp-dma-1.0";
 530                         clock-names = "clk_main", "clk_apb";
 531                         reg = <0x0 0xffac0000 0x0 0x1000>;
 532                         interrupt-parent = <&gic>;
 533                         interrupts = <0 81 4>;
 534                         xlnx,bus-width = <64>;
 535                         #stream-id-cells = <1>;
 536                         iommus = <&smmu 0x86c>;
 537                         power-domains = <&pd_adma>;
 538                 };
 539
 540                 lpd_dma_chan6: dma@ffad0000 {
 541                         status = "disabled";
 542                         compatible = "xlnx,zynqmp-dma-1.0";
 543                         clock-names = "clk_main", "clk_apb";
 544                         reg = <0x0 0xffad0000 0x0 0x1000>;
 545                         interrupt-parent = <&gic>;
 546                         interrupts = <0 82 4>;
 547                         xlnx,bus-width = <64>;
 548                         #stream-id-cells = <1>;
 549                         iommus = <&smmu 0x86d>;
 550                         power-domains = <&pd_adma>;
 551                 };
 552
 553                 lpd_dma_chan7: dma@ffae0000 {
 554                         status = "disabled";
 555                         compatible = "xlnx,zynqmp-dma-1.0";
 556                         clock-names = "clk_main", "clk_apb";
 557                         reg = <0x0 0xffae0000 0x0 0x1000>;
 558                         interrupt-parent = <&gic>;
 559                         interrupts = <0 83 4>;
 560                         xlnx,bus-width = <64>;
 561                         #stream-id-cells = <1>;
 562                         iommus = <&smmu 0x86e>;
 563                         power-domains = <&pd_adma>;
 564                 };
 565
 566                 lpd_dma_chan8: dma@ffaf0000 {
 567                         status = "disabled";
 568                         compatible = "xlnx,zynqmp-dma-1.0";
 569                         clock-names = "clk_main", "clk_apb";
 570                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 571                         interrupt-parent = <&gic>;
 572                         interrupts = <0 84 4>;
 573                         xlnx,bus-width = <64>;
 574                         #stream-id-cells = <1>;
 575                         iommus = <&smmu 0x86f>;
 576                         power-domains = <&pd_adma>;
 577                 };
 578
 579                 mc: memory-controller@fd070000 {
 580                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 581                         reg = <0x0 0xfd070000 0x0 0x30000>;
 582                         interrupt-parent = <&gic>;
 583                         interrupts = <0 112 4>;
 584                 };
 585
 586                 nand0: nand@ff100000 {
 587                         compatible = "arasan,nfc-v3p10";
 588                         status = "disabled";
 589                         reg = <0x0 0xff100000 0x0 0x1000>;
 590                         clock-names = "clk_sys", "clk_flash";
 591                         interrupt-parent = <&gic>;
 592                         interrupts = <0 14 4>;
 593                         #address-cells = <2>;
 594                         #size-cells = <1>;
 595                         #stream-id-cells = <1>;
 596                         iommus = <&smmu 0x872>;
 597                         power-domains = <&pd_nand>;
 598                 };
 599
 600                 gem0: ethernet@ff0b0000 {
 601                         compatible = "cdns,zynqmp-gem";
 602                         status = "disabled";
 603                         interrupt-parent = <&gic>;
 604                         interrupts = <0 57 4>, <0 57 4>;
 605                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 606                         clock-names = "pclk", "hclk", "tx_clk";
 607                         #address-cells = <1>;
 608                         #size-cells = <0>;
 609                         #stream-id-cells = <1>;
 610                         iommus = <&smmu 0x874>;
 611                         power-domains = <&pd_eth0>;
 612                 };
 613
 614                 gem1: ethernet@ff0c0000 {
 615                         compatible = "cdns,zynqmp-gem";
 616                         status = "disabled";
 617                         interrupt-parent = <&gic>;
 618                         interrupts = <0 59 4>, <0 59 4>;
 619                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 620                         clock-names = "pclk", "hclk", "tx_clk";
 621                         #address-cells = <1>;
 622                         #size-cells = <0>;
 623                         #stream-id-cells = <1>;
 624                         iommus = <&smmu 0x875>;
 625                         power-domains = <&pd_eth1>;
 626                 };
 627
 628                 gem2: ethernet@ff0d0000 {
 629                         compatible = "cdns,zynqmp-gem";
 630                         status = "disabled";
 631                         interrupt-parent = <&gic>;
 632                         interrupts = <0 61 4>, <0 61 4>;
 633                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 634                         clock-names = "pclk", "hclk", "tx_clk";
 635                         #address-cells = <1>;
 636                         #size-cells = <0>;
 637                         #stream-id-cells = <1>;
 638                         iommus = <&smmu 0x876>;
 639                         power-domains = <&pd_eth2>;
 640                 };
 641
 642                 gem3: ethernet@ff0e0000 {
 643                         compatible = "cdns,zynqmp-gem";
 644                         status = "disabled";
 645                         interrupt-parent = <&gic>;
 646                         interrupts = <0 63 4>, <0 63 4>;
 647                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 648                         clock-names = "pclk", "hclk", "tx_clk";
 649                         #address-cells = <1>;
 650                         #size-cells = <0>;
 651                         #stream-id-cells = <1>;
 652                         iommus = <&smmu 0x877>;
 653                         power-domains = <&pd_eth3>;
 654                 };
 655
 656                 gpio: gpio@ff0a0000 {
 657                         compatible = "xlnx,zynqmp-gpio-1.0";
 658                         status = "disabled";
 659                         #gpio-cells = <0x2>;
 660                         interrupt-parent = <&gic>;
 661                         interrupts = <0 16 4>;
 662                         interrupt-controller;
 663                         #interrupt-cells = <2>;
 664                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 665                         power-domains = <&pd_gpio>;
 666                 };
 667
 668                 i2c0: i2c@ff020000 {
 669                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 670                         status = "disabled";
 671                         interrupt-parent = <&gic>;
 672                         interrupts = <0 17 4>;
 673                         reg = <0x0 0xff020000 0x0 0x1000>;
 674                         #address-cells = <1>;
 675                         #size-cells = <0>;
 676                         power-domains = <&pd_i2c0>;
 677                 };
 678
 679                 i2c1: i2c@ff030000 {
 680                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 681                         status = "disabled";
 682                         interrupt-parent = <&gic>;
 683                         interrupts = <0 18 4>;
 684                         reg = <0x0 0xff030000 0x0 0x1000>;
 685                         #address-cells = <1>;
 686                         #size-cells = <0>;
 687                         power-domains = <&pd_i2c1>;
 688                 };
 689
 690                 ocm: memory-controller@ff960000 {
 691                         compatible = "xlnx,zynqmp-ocmc-1.0";
 692                         reg = <0x0 0xff960000 0x0 0x1000>;
 693                         interrupt-parent = <&gic>;
 694                         interrupts = <0 10 4>;
 695                 };
 696
 697                 pcie: pcie@fd0e0000 {
 698                         compatible = "xlnx,nwl-pcie-2.11";
 699                         status = "disabled";
 700                         #address-cells = <3>;
 701                         #size-cells = <2>;
 702                         #interrupt-cells = <1>;
 703                         msi-controller;
 704                         device_type = "pci";
 705                         interrupt-parent = <&gic>;
 706                         interrupts = <0 118 4>,
 707                                      <0 117 4>,
 708                                      <0 116 4>,
 709                                      <0 115 4>, /* MSI_1 [63...32] */
 710                                      <0 114 4>; /* MSI_0 [31...0] */
 711                         interrupt-names = "misc","dummy","intx", "msi1", "msi0";
 712                         msi-parent = <&pcie>;
 713                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 714                               <0x0 0xfd480000 0x0 0x1000>,
 715                               <0x80 0x00000000 0x0 0x1000000>;
 716                         reg-names = "breg", "pcireg", "cfg";
 717                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 718                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 719                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 720                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 721                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 722                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 723                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 724                         power-domains = <&pd_pcie>;
 725                         pcie_intc: legacy-interrupt-controller {
 726                                 interrupt-controller;
 727                                 #address-cells = <0>;
 728                                 #interrupt-cells = <1>;
 729                         };
 730                 };
 731
 732                 qspi: spi@ff0f0000 {
 733                         compatible = "xlnx,zynqmp-qspi-1.0";
 734                         status = "disabled";
 735                         clock-names = "ref_clk", "pclk";
 736                         interrupts = <0 15 4>;
 737                         interrupt-parent = <&gic>;
 738                         num-cs = <1>;
 739                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 740                               <0x0 0xc0000000 0x0 0x8000000>;
 741                         #address-cells = <1>;
 742                         #size-cells = <0>;
 743                         #stream-id-cells = <1>;
 744                         iommus = <&smmu 0x873>;
 745                         power-domains = <&pd_qspi>;
 746                 };
 747
 748                 rtc: rtc@ffa60000 {
 749                         compatible = "xlnx,zynqmp-rtc";
 750                         status = "disabled";
 751                         reg = <0x0 0xffa60000 0x0 0x100>;
 752                         interrupt-parent = <&gic>;
 753                         interrupts = <0 26 4>, <0 27 4>;
 754                         interrupt-names = "alarm", "sec";
 755                 };
 756
 757                 serdes: zynqmp_phy@fd400000 {
 758                         compatible = "xlnx,zynqmp-psgtr";
 759                         status = "disabled";
 760                         reg = <0x0 0xfd400000 0x0 0x40000>,
 761                               <0x0 0xfd3d0000 0x0 0x1000>,
 762                               <0x0 0xfd1a0000 0x0 0x1000>,
 763                               <0x0 0xff5e0000 0x0 0x1000>;
 764                         reg-names = "serdes", "siou", "fpd", "lpd";
 765                         xlnx,tx_termination_fix;
 766                         lane0: lane0 {
 767                                 #phy-cells = <4>;
 768                         };
 769                         lane1: lane1 {
 770                                 #phy-cells = <4>;
 771                         };
 772                         lane2: lane2 {
 773                                 #phy-cells = <4>;
 774                         };
 775                         lane3: lane3 {
 776                                 #phy-cells = <4>;
 777                         };
 778                 };
 779
 780                 sata: ahci@fd0c0000 {
 781                         compatible = "ceva,ahci-1v84";
 782                         status = "disabled";
 783                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 784                         interrupt-parent = <&gic>;
 785                         interrupts = <0 133 4>;
 786                         power-domains = <&pd_sata>;
 787                 };
 788
 789                 sdhci0: sdhci@ff160000 {
 790                         u-boot,dm-pre-reloc;
 791                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 792                         status = "disabled";
 793                         interrupt-parent = <&gic>;
 794                         interrupts = <0 48 4>;
 795                         reg = <0x0 0xff160000 0x0 0x1000>;
 796                         clock-names = "clk_xin", "clk_ahb";
 797                         xlnx,device_id = <0>;
 798                         #stream-id-cells = <1>;
 799                         iommus = <&smmu 0x870>;
 800                         power-domains = <&pd_sd0>;
 801                 };
 802
 803                 sdhci1: sdhci@ff170000 {
 804                         u-boot,dm-pre-reloc;
 805                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 806                         status = "disabled";
 807                         interrupt-parent = <&gic>;
 808                         interrupts = <0 49 4>;
 809                         reg = <0x0 0xff170000 0x0 0x1000>;
 810                         clock-names = "clk_xin", "clk_ahb";
 811                         xlnx,device_id = <1>;
 812                         #stream-id-cells = <1>;
 813                         iommus = <&smmu 0x871>;
 814                         power-domains = <&pd_sd1>;
 815                 };
 816
 817                 smmu: smmu@fd800000 {
 818                         compatible = "arm,mmu-500";
 819                         reg = <0x0 0xfd800000 0x0 0x20000>;
 820                         #iommu-cells = <1>;
 821                         #global-interrupts = <1>;
 822                         interrupt-parent = <&gic>;
 823                         interrupts = <0 155 4>,
 824                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 825                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 826                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 827                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 828                         mmu-masters = < &gem0 0x874
 829                                         &gem1 0x875
 830                                         &gem2 0x876
 831                                         &gem3 0x877
 832                                         &usb0 0x860
 833                                         &usb1 0x861
 834                                         &qspi 0x873
 835                                         &lpd_dma_chan1 0x868
 836                                         &lpd_dma_chan2 0x869
 837                                         &lpd_dma_chan3 0x86a
 838                                         &lpd_dma_chan4 0x86b
 839                                         &lpd_dma_chan5 0x86c
 840                                         &lpd_dma_chan6 0x86d
 841                                         &lpd_dma_chan7 0x86e
 842                                         &lpd_dma_chan8 0x86f
 843                                         &fpd_dma_chan1 0x14e8
 844                                         &fpd_dma_chan2 0x14e9
 845                                         &fpd_dma_chan3 0x14ea
 846                                         &fpd_dma_chan4 0x14eb
 847                                         &fpd_dma_chan5 0x14ec
 848                                         &fpd_dma_chan6 0x14ed
 849                                         &fpd_dma_chan7 0x14ee
 850                                         &fpd_dma_chan8 0x14ef
 851                                         &sdhci0 0x870
 852                                         &sdhci1 0x871
 853                                         &nand0 0x872>;
 854                 };
 855
 856                 spi0: spi@ff040000 {
 857                         compatible = "cdns,spi-r1p6";
 858                         status = "disabled";
 859                         interrupt-parent = <&gic>;
 860                         interrupts = <0 19 4>;
 861                         reg = <0x0 0xff040000 0x0 0x1000>;
 862                         clock-names = "ref_clk", "pclk";
 863                         #address-cells = <1>;
 864                         #size-cells = <0>;
 865                         power-domains = <&pd_spi0>;
 866                 };
 867
 868                 spi1: spi@ff050000 {
 869                         compatible = "cdns,spi-r1p6";
 870                         status = "disabled";
 871                         interrupt-parent = <&gic>;
 872                         interrupts = <0 20 4>;
 873                         reg = <0x0 0xff050000 0x0 0x1000>;
 874                         clock-names = "ref_clk", "pclk";
 875                         #address-cells = <1>;
 876                         #size-cells = <0>;
 877                         power-domains = <&pd_spi1>;
 878                 };
 879
 880                 ttc0: timer@ff110000 {
 881                         compatible = "cdns,ttc";
 882                         status = "disabled";
 883                         interrupt-parent = <&gic>;
 884                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 885                         reg = <0x0 0xff110000 0x0 0x1000>;
 886                         timer-width = <32>;
 887                         power-domains = <&pd_ttc0>;
 888                 };
 889
 890                 ttc1: timer@ff120000 {
 891                         compatible = "cdns,ttc";
 892                         status = "disabled";
 893                         interrupt-parent = <&gic>;
 894                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 895                         reg = <0x0 0xff120000 0x0 0x1000>;
 896                         timer-width = <32>;
 897                         power-domains = <&pd_ttc1>;
 898                 };
 899
 900                 ttc2: timer@ff130000 {
 901                         compatible = "cdns,ttc";
 902                         status = "disabled";
 903                         interrupt-parent = <&gic>;
 904                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 905                         reg = <0x0 0xff130000 0x0 0x1000>;
 906                         timer-width = <32>;
 907                         power-domains = <&pd_ttc2>;
 908                 };
 909
 910                 ttc3: timer@ff140000 {
 911                         compatible = "cdns,ttc";
 912                         status = "disabled";
 913                         interrupt-parent = <&gic>;
 914                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 915                         reg = <0x0 0xff140000 0x0 0x1000>;
 916                         timer-width = <32>;
 917                         power-domains = <&pd_ttc3>;
 918                 };
 919
 920                 uart0: serial@ff000000 {
 921                         u-boot,dm-pre-reloc;
 922                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 923                         status = "disabled";
 924                         interrupt-parent = <&gic>;
 925                         interrupts = <0 21 4>;
 926                         reg = <0x0 0xff000000 0x0 0x1000>;
 927                         clock-names = "uart_clk", "pclk";
 928                         power-domains = <&pd_uart0>;
 929                 };
 930
 931                 uart1: serial@ff010000 {
 932                         u-boot,dm-pre-reloc;
 933                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 934                         status = "disabled";
 935                         interrupt-parent = <&gic>;
 936                         interrupts = <0 22 4>;
 937                         reg = <0x0 0xff010000 0x0 0x1000>;
 938                         clock-names = "uart_clk", "pclk";
 939                         power-domains = <&pd_uart1>;
 940                 };
 941
 942                 usb0: usb0 {
 943                         #address-cells = <2>;
 944                         #size-cells = <2>;
 945                         status = "disabled";
 946                         compatible = "xlnx,zynqmp-dwc3";
 947                         clock-names = "bus_clk", "ref_clk";
 948                         clocks = <&clk125>, <&clk125>;
 949                         #stream-id-cells = <1>;
 950                         iommus = <&smmu 0x860>;
 951                         power-domains = <&pd_usb0>;
 952                         ranges;
 953
 954                         dwc3_0: dwc3@fe200000 {
 955                                 compatible = "snps,dwc3";
 956                                 status = "disabled";
 957                                 reg = <0x0 0xfe200000 0x0 0x40000>;
 958                                 interrupt-parent = <&gic>;
 959                                 interrupts = <0 65 4>;
 960                                 /* snps,quirk-frame-length-adjustment = <0x20>; */
 961                                 snps,refclk_fladj;
 962                         };
 963                 };
 964
 965                 usb1: usb1 {
 966                         #address-cells = <2>;
 967                         #size-cells = <2>;
 968                         status = "disabled";
 969                         compatible = "xlnx,zynqmp-dwc3";
 970                         clock-names = "bus_clk", "ref_clk";
 971                         clocks = <&clk125>, <&clk125>;
 972                         #stream-id-cells = <1>;
 973                         iommus = <&smmu 0x861>;
 974                         power-domains = <&pd_usb1>;
 975                         ranges;
 976
 977                         dwc3_1: dwc3@fe300000 {
 978                                 compatible = "snps,dwc3";
 979                                 status = "disabled";
 980                                 reg = <0x0 0xfe300000 0x0 0x40000>;
 981                                 interrupt-parent = <&gic>;
 982                                 interrupts = <0 70 4>;
 983                                 /* snps,quirk-frame-length-adjustment = <0x20>; */
 984                                 snps,refclk_fladj;
 985                         };
 986                 };
 987
 988                 watchdog0: watchdog@fd4d0000 {
 989                         compatible = "cdns,wdt-r1p2";
 990                         status = "disabled";
 991                         interrupt-parent = <&gic>;
 992                         interrupts = <0 113 1>;
 993                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
 994                         timeout-sec = <10>;
 995                 };
 996
 997                 xilinx_drm: xilinx_drm {
 998                         compatible = "xlnx,drm";
 999                         status = "disabled";
1000                         xlnx,encoder-slave = <&xlnx_dp>;
1001                         xlnx,connector-type = "DisplayPort";
1002                         xlnx,dp-sub = <&xlnx_dp_sub>;
1003                         planes {
1004                                 xlnx,pixel-format = "rgb565";
1005                                 plane0 {
1006                                         dmas = <&xlnx_dpdma 3>;
1007                                         dma-names = "dma0";
1008                                 };
1009                                 plane1 {
1010                                         dmas = <&xlnx_dpdma 0>,
1011                                                <&xlnx_dpdma 1>,
1012                                                <&xlnx_dpdma 2>;
1013                                         dma-names = "dma0", "dma1", "dma2";
1014                                 };
1015                         };
1016                 };
1017
1018                 xlnx_dp: dp@fd4a0000 {
1019                         compatible = "xlnx,v-dp";
1020                         status = "disabled";
1021                         reg = <0x0 0xfd4a0000 0x0 0x1000>;
1022                         interrupts = <0 119 4>;
1023                         interrupt-parent = <&gic>;
1024                         clock-names = "aclk", "aud_clk";
1025                         xlnx,dp-version = "v1.2";
1026                         xlnx,max-lanes = <2>;
1027                         xlnx,max-link-rate = <540000>;
1028                         xlnx,max-bpc = <16>;
1029                         xlnx,enable-ycrcb;
1030                         xlnx,colormetry = "rgb";
1031                         xlnx,bpc = <8>;
1032                         xlnx,audio-chan = <2>;
1033                         xlnx,dp-sub = <&xlnx_dp_sub>;
1034                         xlnx,max-pclock-frequency = <300000>;
1035                 };
1036
1037                 xlnx_dp_snd_card: dp_snd_card {
1038                         compatible = "xlnx,dp-snd-card";
1039                         status = "disabled";
1040                         xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
1041                         xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
1042                 };
1043
1044                 xlnx_dp_snd_codec0: dp_snd_codec0 {
1045                         compatible = "xlnx,dp-snd-codec";
1046                         status = "disabled";
1047                         clock-names = "aud_clk";
1048                 };
1049
1050                 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
1051                         compatible = "xlnx,dp-snd-pcm";
1052                         status = "disabled";
1053                         dmas = <&xlnx_dpdma 4>;
1054                         dma-names = "tx";
1055                 };
1056
1057                 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1058                         compatible = "xlnx,dp-snd-pcm";
1059                         status = "disabled";
1060                         dmas = <&xlnx_dpdma 5>;
1061                         dma-names = "tx";
1062                 };
1063
1064                 xlnx_dp_sub: dp_sub@fd4aa000 {
1065                         compatible = "xlnx,dp-sub";
1066                         status = "disabled";
1067                         reg = <0x0 0xfd4aa000 0x0 0x1000>,
1068                               <0x0 0xfd4ab000 0x0 0x1000>,
1069                               <0x0 0xfd4ac000 0x0 0x1000>;
1070                         reg-names = "blend", "av_buf", "aud";
1071                         xlnx,output-fmt = "rgb";
1072                         xlnx,vid-fmt = "yuyv";
1073                         xlnx,gfx-fmt = "rgb565";
1074                 };
1075
1076                 xlnx_dpdma: dma@fd4c0000 {
1077                         compatible = "xlnx,dpdma";
1078                         status = "disabled";
1079                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
1080                         interrupts = <0 122 4>;
1081                         interrupt-parent = <&gic>;
1082                         clock-names = "axi_clk";
1083                         dma-channels = <6>;
1084                         #dma-cells = <1>;
1085                         dma-video0channel {
1086                                 compatible = "xlnx,video0";
1087                         };
1088                         dma-video1channel {
1089                                 compatible = "xlnx,video1";
1090                         };
1091                         dma-video2channel {
1092                                 compatible = "xlnx,video2";
1093                         };
1094                         dma-graphicschannel {
1095                                 compatible = "xlnx,graphics";
1096                         };
1097                         dma-audio0channel {
1098                                 compatible = "xlnx,audio0";
1099                         };
1100                         dma-audio1channel {
1101                                 compatible = "xlnx,audio1";
1102                         };
1103                 };
1104         };
1105 };