1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2020, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
19 compatible = "xlnx,zynqmp";
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
31 operating-points-v2 = <&cpu_opp_table>;
33 cpu-idle-states = <&CPU_SLEEP_0>;
37 compatible = "arm,cortex-a53";
39 enable-method = "psci";
41 operating-points-v2 = <&cpu_opp_table>;
42 cpu-idle-states = <&CPU_SLEEP_0>;
46 compatible = "arm,cortex-a53";
48 enable-method = "psci";
50 operating-points-v2 = <&cpu_opp_table>;
51 cpu-idle-states = <&CPU_SLEEP_0>;
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
59 operating-points-v2 = <&cpu_opp_table>;
60 cpu-idle-states = <&CPU_SLEEP_0>;
64 entry-method = "psci";
66 CPU_SLEEP_0: cpu-sleep-0 {
67 compatible = "arm,idle-state";
68 arm,psci-suspend-param = <0x40000000>;
70 entry-latency-us = <300>;
71 exit-latency-us = <600>;
72 min-residency-us = <10000>;
77 cpu_opp_table: cpu-opp-table {
78 compatible = "operating-points-v2";
81 opp-hz = /bits/ 64 <1199999988>;
82 opp-microvolt = <1000000>;
83 clock-latency-ns = <500000>;
86 opp-hz = /bits/ 64 <599999994>;
87 opp-microvolt = <1000000>;
88 clock-latency-ns = <500000>;
91 opp-hz = /bits/ 64 <399999996>;
92 opp-microvolt = <1000000>;
93 clock-latency-ns = <500000>;
96 opp-hz = /bits/ 64 <299999997>;
97 opp-microvolt = <1000000>;
98 clock-latency-ns = <500000>;
104 compatible = "xlnx,zynqmp-ipi-mailbox";
105 interrupt-parent = <&gic>;
106 interrupts = <0 35 4>;
108 #address-cells = <2>;
112 ipi_mailbox_pmu1: mailbox@ff990400 {
114 reg = <0x0 0xff9905c0 0x0 0x20>,
115 <0x0 0xff9905e0 0x0 0x20>,
116 <0x0 0xff990e80 0x0 0x20>,
117 <0x0 0xff990ea0 0x0 0x20>;
118 reg-names = "local_request_region", "local_response_region",
119 "remote_request_region", "remote_response_region";
126 compatible = "arm,dcc";
132 compatible = "arm,armv8-pmuv3";
133 interrupt-parent = <&gic>;
134 interrupts = <0 143 4>,
141 compatible = "arm,psci-0.2";
146 zynqmp_firmware: zynqmp-firmware {
147 compatible = "xlnx,zynqmp-firmware";
149 #power-domain-cells = <0x1>;
153 compatible = "xlnx,zynqmp-pcap-fpga";
154 clock-names = "ref_clk";
157 zynqmp_power: zynqmp-power {
159 compatible = "xlnx,zynqmp-power";
160 interrupt-parent = <&gic>;
161 interrupts = <0 35 4>;
162 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
163 mbox-names = "tx", "rx";
166 zynqmp_reset: reset-controller {
167 compatible = "xlnx,zynqmp-reset";
174 compatible = "arm,armv8-timer";
175 interrupt-parent = <&gic>;
176 interrupts = <1 13 0xf08>,
183 compatible = "arm,cortex-a53-edac";
186 fpga_full: fpga-full {
187 compatible = "fpga-region";
188 fpga-mgr = <&zynqmp_pcap>;
189 #address-cells = <2>;
195 compatible = "xlnx,zynqmp-nvmem-fw";
196 #address-cells = <1>;
199 soc_revision: soc_revision@0 {
204 xlnx_dp_snd_card: dp_snd_card {
205 compatible = "xlnx,dp-snd-card";
207 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
208 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
211 xlnx_dp_snd_codec0: dp_snd_codec0 {
212 compatible = "xlnx,dp-snd-codec";
214 clock-names = "aud_clk";
217 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
218 compatible = "xlnx,dp-snd-pcm";
220 dmas = <&xlnx_dpdma 4>;
224 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
225 compatible = "xlnx,dp-snd-pcm";
227 dmas = <&xlnx_dpdma 5>;
231 xilinx_drm: xilinx_drm {
232 compatible = "xlnx,drm";
234 xlnx,encoder-slave = <&xlnx_dp>;
235 xlnx,connector-type = "DisplayPort";
236 xlnx,dp-sub = <&xlnx_dp_sub>;
238 xlnx,pixel-format = "rgb565";
240 dmas = <&xlnx_dpdma 3>;
244 dmas = <&xlnx_dpdma 0>,
247 dma-names = "dma0", "dma1", "dma2";
252 amba_apu: amba-apu@0 {
253 compatible = "simple-bus";
254 #address-cells = <2>;
256 ranges = <0 0 0 0 0xffffffff>;
258 gic: interrupt-controller@f9010000 {
259 compatible = "arm,gic-400", "arm,cortex-a15-gic";
260 #interrupt-cells = <3>;
261 reg = <0x0 0xf9010000 0x10000>,
262 <0x0 0xf9020000 0x20000>,
263 <0x0 0xf9040000 0x20000>,
264 <0x0 0xf9060000 0x20000>;
265 interrupt-controller;
266 interrupt-parent = <&gic>;
267 interrupts = <1 9 0xf04>;
272 compatible = "simple-bus";
274 #address-cells = <2>;
279 compatible = "xlnx,zynq-can-1.0";
281 clock-names = "can_clk", "pclk";
282 reg = <0x0 0xff060000 0x0 0x1000>;
283 interrupts = <0 23 4>;
284 interrupt-parent = <&gic>;
285 tx-fifo-depth = <0x40>;
286 rx-fifo-depth = <0x40>;
287 power-domains = <&zynqmp_firmware PD_CAN_0>;
291 compatible = "xlnx,zynq-can-1.0";
293 clock-names = "can_clk", "pclk";
294 reg = <0x0 0xff070000 0x0 0x1000>;
295 interrupts = <0 24 4>;
296 interrupt-parent = <&gic>;
297 tx-fifo-depth = <0x40>;
298 rx-fifo-depth = <0x40>;
299 power-domains = <&zynqmp_firmware PD_CAN_1>;
303 compatible = "arm,cci-400";
304 reg = <0x0 0xfd6e0000 0x0 0x9000>;
305 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
306 #address-cells = <1>;
310 compatible = "arm,cci-400-pmu,r1";
311 reg = <0x9000 0x5000>;
312 interrupt-parent = <&gic>;
313 interrupts = <0 123 4>,
322 fpd_dma_chan1: dma@fd500000 {
324 compatible = "xlnx,zynqmp-dma-1.0";
325 reg = <0x0 0xfd500000 0x0 0x1000>;
326 interrupt-parent = <&gic>;
327 interrupts = <0 124 4>;
328 clock-names = "clk_main", "clk_apb";
329 xlnx,bus-width = <128>;
330 #stream-id-cells = <1>;
331 iommus = <&smmu 0x14e8>;
332 power-domains = <&zynqmp_firmware PD_GDMA>;
335 fpd_dma_chan2: dma@fd510000 {
337 compatible = "xlnx,zynqmp-dma-1.0";
338 reg = <0x0 0xfd510000 0x0 0x1000>;
339 interrupt-parent = <&gic>;
340 interrupts = <0 125 4>;
341 clock-names = "clk_main", "clk_apb";
342 xlnx,bus-width = <128>;
343 #stream-id-cells = <1>;
344 iommus = <&smmu 0x14e9>;
345 power-domains = <&zynqmp_firmware PD_GDMA>;
348 fpd_dma_chan3: dma@fd520000 {
350 compatible = "xlnx,zynqmp-dma-1.0";
351 reg = <0x0 0xfd520000 0x0 0x1000>;
352 interrupt-parent = <&gic>;
353 interrupts = <0 126 4>;
354 clock-names = "clk_main", "clk_apb";
355 xlnx,bus-width = <128>;
356 #stream-id-cells = <1>;
357 iommus = <&smmu 0x14ea>;
358 power-domains = <&zynqmp_firmware PD_GDMA>;
361 fpd_dma_chan4: dma@fd530000 {
363 compatible = "xlnx,zynqmp-dma-1.0";
364 reg = <0x0 0xfd530000 0x0 0x1000>;
365 interrupt-parent = <&gic>;
366 interrupts = <0 127 4>;
367 clock-names = "clk_main", "clk_apb";
368 xlnx,bus-width = <128>;
369 #stream-id-cells = <1>;
370 iommus = <&smmu 0x14eb>;
371 power-domains = <&zynqmp_firmware PD_GDMA>;
374 fpd_dma_chan5: dma@fd540000 {
376 compatible = "xlnx,zynqmp-dma-1.0";
377 reg = <0x0 0xfd540000 0x0 0x1000>;
378 interrupt-parent = <&gic>;
379 interrupts = <0 128 4>;
380 clock-names = "clk_main", "clk_apb";
381 xlnx,bus-width = <128>;
382 #stream-id-cells = <1>;
383 iommus = <&smmu 0x14ec>;
384 power-domains = <&zynqmp_firmware PD_GDMA>;
387 fpd_dma_chan6: dma@fd550000 {
389 compatible = "xlnx,zynqmp-dma-1.0";
390 reg = <0x0 0xfd550000 0x0 0x1000>;
391 interrupt-parent = <&gic>;
392 interrupts = <0 129 4>;
393 clock-names = "clk_main", "clk_apb";
394 xlnx,bus-width = <128>;
395 #stream-id-cells = <1>;
396 iommus = <&smmu 0x14ed>;
397 power-domains = <&zynqmp_firmware PD_GDMA>;
400 fpd_dma_chan7: dma@fd560000 {
402 compatible = "xlnx,zynqmp-dma-1.0";
403 reg = <0x0 0xfd560000 0x0 0x1000>;
404 interrupt-parent = <&gic>;
405 interrupts = <0 130 4>;
406 clock-names = "clk_main", "clk_apb";
407 xlnx,bus-width = <128>;
408 #stream-id-cells = <1>;
409 iommus = <&smmu 0x14ee>;
410 power-domains = <&zynqmp_firmware PD_GDMA>;
413 fpd_dma_chan8: dma@fd570000 {
415 compatible = "xlnx,zynqmp-dma-1.0";
416 reg = <0x0 0xfd570000 0x0 0x1000>;
417 interrupt-parent = <&gic>;
418 interrupts = <0 131 4>;
419 clock-names = "clk_main", "clk_apb";
420 xlnx,bus-width = <128>;
421 #stream-id-cells = <1>;
422 iommus = <&smmu 0x14ef>;
423 power-domains = <&zynqmp_firmware PD_GDMA>;
428 compatible = "arm,mali-400", "arm,mali-utgard";
429 reg = <0x0 0xfd4b0000 0x0 0x10000>;
430 interrupt-parent = <&gic>;
431 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
432 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
433 clock-names = "gpu", "gpu_pp0", "gpu_pp1";
434 power-domains = <&zynqmp_firmware PD_GPU>;
437 /* LPDDMA default allows only secured access. inorder to enable
438 * These dma channels, Users should ensure that these dma
439 * Channels are allowed for non secure access.
441 lpd_dma_chan1: dma@ffa80000 {
443 compatible = "xlnx,zynqmp-dma-1.0";
444 reg = <0x0 0xffa80000 0x0 0x1000>;
445 interrupt-parent = <&gic>;
446 interrupts = <0 77 4>;
447 clock-names = "clk_main", "clk_apb";
448 xlnx,bus-width = <64>;
449 #stream-id-cells = <1>;
450 iommus = <&smmu 0x868>;
451 power-domains = <&zynqmp_firmware PD_ADMA>;
454 lpd_dma_chan2: dma@ffa90000 {
456 compatible = "xlnx,zynqmp-dma-1.0";
457 reg = <0x0 0xffa90000 0x0 0x1000>;
458 interrupt-parent = <&gic>;
459 interrupts = <0 78 4>;
460 clock-names = "clk_main", "clk_apb";
461 xlnx,bus-width = <64>;
462 #stream-id-cells = <1>;
463 iommus = <&smmu 0x869>;
464 power-domains = <&zynqmp_firmware PD_ADMA>;
467 lpd_dma_chan3: dma@ffaa0000 {
469 compatible = "xlnx,zynqmp-dma-1.0";
470 reg = <0x0 0xffaa0000 0x0 0x1000>;
471 interrupt-parent = <&gic>;
472 interrupts = <0 79 4>;
473 clock-names = "clk_main", "clk_apb";
474 xlnx,bus-width = <64>;
475 #stream-id-cells = <1>;
476 iommus = <&smmu 0x86a>;
477 power-domains = <&zynqmp_firmware PD_ADMA>;
480 lpd_dma_chan4: dma@ffab0000 {
482 compatible = "xlnx,zynqmp-dma-1.0";
483 reg = <0x0 0xffab0000 0x0 0x1000>;
484 interrupt-parent = <&gic>;
485 interrupts = <0 80 4>;
486 clock-names = "clk_main", "clk_apb";
487 xlnx,bus-width = <64>;
488 #stream-id-cells = <1>;
489 iommus = <&smmu 0x86b>;
490 power-domains = <&zynqmp_firmware PD_ADMA>;
493 lpd_dma_chan5: dma@ffac0000 {
495 compatible = "xlnx,zynqmp-dma-1.0";
496 reg = <0x0 0xffac0000 0x0 0x1000>;
497 interrupt-parent = <&gic>;
498 interrupts = <0 81 4>;
499 clock-names = "clk_main", "clk_apb";
500 xlnx,bus-width = <64>;
501 #stream-id-cells = <1>;
502 iommus = <&smmu 0x86c>;
503 power-domains = <&zynqmp_firmware PD_ADMA>;
506 lpd_dma_chan6: dma@ffad0000 {
508 compatible = "xlnx,zynqmp-dma-1.0";
509 reg = <0x0 0xffad0000 0x0 0x1000>;
510 interrupt-parent = <&gic>;
511 interrupts = <0 82 4>;
512 clock-names = "clk_main", "clk_apb";
513 xlnx,bus-width = <64>;
514 #stream-id-cells = <1>;
515 iommus = <&smmu 0x86d>;
516 power-domains = <&zynqmp_firmware PD_ADMA>;
519 lpd_dma_chan7: dma@ffae0000 {
521 compatible = "xlnx,zynqmp-dma-1.0";
522 reg = <0x0 0xffae0000 0x0 0x1000>;
523 interrupt-parent = <&gic>;
524 interrupts = <0 83 4>;
525 clock-names = "clk_main", "clk_apb";
526 xlnx,bus-width = <64>;
527 #stream-id-cells = <1>;
528 iommus = <&smmu 0x86e>;
529 power-domains = <&zynqmp_firmware PD_ADMA>;
532 lpd_dma_chan8: dma@ffaf0000 {
534 compatible = "xlnx,zynqmp-dma-1.0";
535 reg = <0x0 0xffaf0000 0x0 0x1000>;
536 interrupt-parent = <&gic>;
537 interrupts = <0 84 4>;
538 clock-names = "clk_main", "clk_apb";
539 xlnx,bus-width = <64>;
540 #stream-id-cells = <1>;
541 iommus = <&smmu 0x86f>;
542 power-domains = <&zynqmp_firmware PD_ADMA>;
545 mc: memory-controller@fd070000 {
546 compatible = "xlnx,zynqmp-ddrc-2.40a";
547 reg = <0x0 0xfd070000 0x0 0x30000>;
548 interrupt-parent = <&gic>;
549 interrupts = <0 112 4>;
552 nand0: nand@ff100000 {
553 compatible = "arasan,nfc-v3p10";
555 reg = <0x0 0xff100000 0x0 0x1000>;
556 clock-names = "clk_sys", "clk_flash";
557 interrupt-parent = <&gic>;
558 interrupts = <0 14 4>;
559 #address-cells = <1>;
561 #stream-id-cells = <1>;
562 iommus = <&smmu 0x872>;
563 power-domains = <&zynqmp_firmware PD_NAND>;
566 gem0: ethernet@ff0b0000 {
567 compatible = "cdns,zynqmp-gem", "cdns,gem";
569 interrupt-parent = <&gic>;
570 interrupts = <0 57 4>, <0 57 4>;
571 reg = <0x0 0xff0b0000 0x0 0x1000>;
572 clock-names = "pclk", "hclk", "tx_clk";
573 #address-cells = <1>;
575 #stream-id-cells = <1>;
576 iommus = <&smmu 0x874>;
577 power-domains = <&zynqmp_firmware PD_ETH_0>;
580 gem1: ethernet@ff0c0000 {
581 compatible = "cdns,zynqmp-gem", "cdns,gem";
583 interrupt-parent = <&gic>;
584 interrupts = <0 59 4>, <0 59 4>;
585 reg = <0x0 0xff0c0000 0x0 0x1000>;
586 clock-names = "pclk", "hclk", "tx_clk";
587 #address-cells = <1>;
589 #stream-id-cells = <1>;
590 iommus = <&smmu 0x875>;
591 power-domains = <&zynqmp_firmware PD_ETH_1>;
594 gem2: ethernet@ff0d0000 {
595 compatible = "cdns,zynqmp-gem", "cdns,gem";
597 interrupt-parent = <&gic>;
598 interrupts = <0 61 4>, <0 61 4>;
599 reg = <0x0 0xff0d0000 0x0 0x1000>;
600 clock-names = "pclk", "hclk", "tx_clk";
601 #address-cells = <1>;
603 #stream-id-cells = <1>;
604 iommus = <&smmu 0x876>;
605 power-domains = <&zynqmp_firmware PD_ETH_2>;
608 gem3: ethernet@ff0e0000 {
609 compatible = "cdns,zynqmp-gem", "cdns,gem";
611 interrupt-parent = <&gic>;
612 interrupts = <0 63 4>, <0 63 4>;
613 reg = <0x0 0xff0e0000 0x0 0x1000>;
614 clock-names = "pclk", "hclk", "tx_clk";
615 #address-cells = <1>;
617 #stream-id-cells = <1>;
618 iommus = <&smmu 0x877>;
619 power-domains = <&zynqmp_firmware PD_ETH_3>;
622 gpio: gpio@ff0a0000 {
623 compatible = "xlnx,zynqmp-gpio-1.0";
627 interrupt-parent = <&gic>;
628 interrupts = <0 16 4>;
629 interrupt-controller;
630 #interrupt-cells = <2>;
631 reg = <0x0 0xff0a0000 0x0 0x1000>;
632 power-domains = <&zynqmp_firmware PD_GPIO>;
636 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
638 interrupt-parent = <&gic>;
639 interrupts = <0 17 4>;
640 reg = <0x0 0xff020000 0x0 0x1000>;
641 #address-cells = <1>;
643 power-domains = <&zynqmp_firmware PD_I2C_0>;
647 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
649 interrupt-parent = <&gic>;
650 interrupts = <0 18 4>;
651 reg = <0x0 0xff030000 0x0 0x1000>;
652 #address-cells = <1>;
654 power-domains = <&zynqmp_firmware PD_I2C_1>;
657 ocm: memory-controller@ff960000 {
658 compatible = "xlnx,zynqmp-ocmc-1.0";
659 reg = <0x0 0xff960000 0x0 0x1000>;
660 interrupt-parent = <&gic>;
661 interrupts = <0 10 4>;
664 pcie: pcie@fd0e0000 {
665 compatible = "xlnx,nwl-pcie-2.11";
667 #address-cells = <3>;
669 #interrupt-cells = <1>;
672 interrupt-parent = <&gic>;
673 interrupts = <0 118 4>,
676 <0 115 4>, /* MSI_1 [63...32] */
677 <0 114 4>; /* MSI_0 [31...0] */
678 interrupt-names = "misc", "dummy", "intx",
680 msi-parent = <&pcie>;
681 reg = <0x0 0xfd0e0000 0x0 0x1000>,
682 <0x0 0xfd480000 0x0 0x1000>,
683 <0x80 0x00000000 0x0 0x1000000>;
684 reg-names = "breg", "pcireg", "cfg";
685 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
686 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
687 bus-range = <0x00 0xff>;
688 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
689 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
690 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
691 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
692 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
693 power-domains = <&zynqmp_firmware PD_PCIE>;
694 pcie_intc: legacy-interrupt-controller {
695 interrupt-controller;
696 #address-cells = <0>;
697 #interrupt-cells = <1>;
703 compatible = "xlnx,zynqmp-qspi-1.0";
705 clock-names = "ref_clk", "pclk";
706 interrupts = <0 15 4>;
707 interrupt-parent = <&gic>;
709 reg = <0x0 0xff0f0000 0x0 0x1000>,
710 <0x0 0xc0000000 0x0 0x8000000>;
711 #address-cells = <1>;
713 #stream-id-cells = <1>;
714 iommus = <&smmu 0x873>;
715 power-domains = <&zynqmp_firmware PD_QSPI>;
719 compatible = "xlnx,zynqmp-rtc";
721 reg = <0x0 0xffa60000 0x0 0x100>;
722 interrupt-parent = <&gic>;
723 interrupts = <0 26 4>, <0 27 4>;
724 interrupt-names = "alarm", "sec";
725 calibration = <0x8000>;
728 serdes: zynqmp_phy@fd400000 {
729 compatible = "xlnx,zynqmp-psgtr";
731 reg = <0x0 0xfd400000 0x0 0x40000>,
732 <0x0 0xfd3d0000 0x0 0x1000>,
733 <0x0 0xff5e0000 0x0 0x1000>;
734 reg-names = "serdes", "siou", "lpd";
735 nvmem-cells = <&soc_revision>;
736 nvmem-cell-names = "soc_revision";
737 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>,
738 <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
739 <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
740 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
741 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
742 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>,
743 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>,
744 <&zynqmp_reset ZYNQMP_RESET_DP>,
745 <&zynqmp_reset ZYNQMP_RESET_GEM0>,
746 <&zynqmp_reset ZYNQMP_RESET_GEM1>,
747 <&zynqmp_reset ZYNQMP_RESET_GEM2>,
748 <&zynqmp_reset ZYNQMP_RESET_GEM3>;
749 reset-names = "sata_rst", "usb0_crst", "usb1_crst",
750 "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
751 "usb1_apbrst", "dp_rst", "gem0_rst",
752 "gem1_rst", "gem2_rst", "gem3_rst";
767 sata: ahci@fd0c0000 {
768 compatible = "ceva,ahci-1v84";
770 reg = <0x0 0xfd0c0000 0x0 0x2000>;
771 interrupt-parent = <&gic>;
772 interrupts = <0 133 4>;
773 power-domains = <&zynqmp_firmware PD_SATA>;
774 #stream-id-cells = <4>;
775 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
776 <&smmu 0x4c2>, <&smmu 0x4c3>;
780 sdhci0: mmc@ff160000 {
782 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
784 interrupt-parent = <&gic>;
785 interrupts = <0 48 4>;
786 reg = <0x0 0xff160000 0x0 0x1000>;
787 clock-names = "clk_xin", "clk_ahb";
788 xlnx,device_id = <0>;
789 #stream-id-cells = <1>;
790 iommus = <&smmu 0x870>;
791 power-domains = <&zynqmp_firmware PD_SD_0>;
792 nvmem-cells = <&soc_revision>;
793 nvmem-cell-names = "soc_revision";
795 clock-output-names = "clk_out_sd0", "clk_in_sd0";
798 sdhci1: mmc@ff170000 {
800 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
802 interrupt-parent = <&gic>;
803 interrupts = <0 49 4>;
804 reg = <0x0 0xff170000 0x0 0x1000>;
805 clock-names = "clk_xin", "clk_ahb";
806 xlnx,device_id = <1>;
807 #stream-id-cells = <1>;
808 iommus = <&smmu 0x871>;
809 power-domains = <&zynqmp_firmware PD_SD_1>;
810 nvmem-cells = <&soc_revision>;
811 nvmem-cell-names = "soc_revision";
813 clock-output-names = "clk_out_sd1", "clk_in_sd1";
816 pinctrl0: pinctrl@ff180000 {
817 compatible = "xlnx,pinctrl-zynqmp";
819 reg = <0x0 0xff180000 0x0 0x1000>;
822 smmu: smmu@fd800000 {
823 compatible = "arm,mmu-500";
824 reg = <0x0 0xfd800000 0x0 0x20000>;
827 #global-interrupts = <1>;
828 interrupt-parent = <&gic>;
829 interrupts = <0 155 4>,
830 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
831 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
832 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
833 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
837 compatible = "cdns,spi-r1p6";
839 interrupt-parent = <&gic>;
840 interrupts = <0 19 4>;
841 reg = <0x0 0xff040000 0x0 0x1000>;
842 clock-names = "ref_clk", "pclk";
843 #address-cells = <1>;
845 power-domains = <&zynqmp_firmware PD_SPI_0>;
849 compatible = "cdns,spi-r1p6";
851 interrupt-parent = <&gic>;
852 interrupts = <0 20 4>;
853 reg = <0x0 0xff050000 0x0 0x1000>;
854 clock-names = "ref_clk", "pclk";
855 #address-cells = <1>;
857 power-domains = <&zynqmp_firmware PD_SPI_1>;
860 ttc0: timer@ff110000 {
861 compatible = "cdns,ttc";
863 interrupt-parent = <&gic>;
864 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
865 reg = <0x0 0xff110000 0x0 0x1000>;
867 power-domains = <&zynqmp_firmware PD_TTC_0>;
870 ttc1: timer@ff120000 {
871 compatible = "cdns,ttc";
873 interrupt-parent = <&gic>;
874 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
875 reg = <0x0 0xff120000 0x0 0x1000>;
877 power-domains = <&zynqmp_firmware PD_TTC_1>;
880 ttc2: timer@ff130000 {
881 compatible = "cdns,ttc";
883 interrupt-parent = <&gic>;
884 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
885 reg = <0x0 0xff130000 0x0 0x1000>;
887 power-domains = <&zynqmp_firmware PD_TTC_2>;
890 ttc3: timer@ff140000 {
891 compatible = "cdns,ttc";
893 interrupt-parent = <&gic>;
894 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
895 reg = <0x0 0xff140000 0x0 0x1000>;
897 power-domains = <&zynqmp_firmware PD_TTC_3>;
900 uart0: serial@ff000000 {
902 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
904 interrupt-parent = <&gic>;
905 interrupts = <0 21 4>;
906 reg = <0x0 0xff000000 0x0 0x1000>;
907 clock-names = "uart_clk", "pclk";
908 power-domains = <&zynqmp_firmware PD_UART_0>;
911 uart1: serial@ff010000 {
913 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
915 interrupt-parent = <&gic>;
916 interrupts = <0 22 4>;
917 reg = <0x0 0xff010000 0x0 0x1000>;
918 clock-names = "uart_clk", "pclk";
919 power-domains = <&zynqmp_firmware PD_UART_1>;
922 usb0: usb0@ff9d0000 {
923 #address-cells = <2>;
926 compatible = "xlnx,zynqmp-dwc3";
927 reg = <0x0 0xff9d0000 0x0 0x100>;
928 clock-names = "bus_clk", "ref_clk";
929 power-domains = <&zynqmp_firmware PD_USB_0>;
931 nvmem-cells = <&soc_revision>;
932 nvmem-cell-names = "soc_revision";
934 dwc3_0: dwc3@fe200000 {
935 compatible = "snps,dwc3";
937 reg = <0x0 0xfe200000 0x0 0x40000>;
938 interrupt-parent = <&gic>;
939 interrupts = <0 65 4>, <0 69 4>;
940 #stream-id-cells = <1>;
941 iommus = <&smmu 0x860>;
942 snps,quirk-frame-length-adjustment = <0x20>;
948 usb1: usb1@ff9e0000 {
949 #address-cells = <2>;
952 compatible = "xlnx,zynqmp-dwc3";
953 reg = <0x0 0xff9e0000 0x0 0x100>;
954 clock-names = "bus_clk", "ref_clk";
955 power-domains = <&zynqmp_firmware PD_USB_1>;
957 nvmem-cells = <&soc_revision>;
958 nvmem-cell-names = "soc_revision";
960 dwc3_1: dwc3@fe300000 {
961 compatible = "snps,dwc3";
963 reg = <0x0 0xfe300000 0x0 0x40000>;
964 interrupt-parent = <&gic>;
965 interrupts = <0 70 4>, <0 74 4>;
966 #stream-id-cells = <1>;
967 iommus = <&smmu 0x861>;
968 snps,quirk-frame-length-adjustment = <0x20>;
974 watchdog0: watchdog@fd4d0000 {
975 compatible = "cdns,wdt-r1p2";
977 interrupt-parent = <&gic>;
978 interrupts = <0 113 1>;
979 reg = <0x0 0xfd4d0000 0x0 0x1000>;
984 lpd_watchdog: watchdog@ff150000 {
985 compatible = "cdns,wdt-r1p2";
987 interrupt-parent = <&gic>;
988 interrupts = <0 52 1>;
989 reg = <0x0 0xff150000 0x0 0x1000>;
993 xilinx_ams: ams@ffa50000 {
994 compatible = "xlnx,zynqmp-ams";
996 interrupt-parent = <&gic>;
997 interrupts = <0 56 4>;
998 interrupt-names = "ams-irq";
999 reg = <0x0 0xffa50000 0x0 0x800>;
1000 reg-names = "ams-base";
1001 #address-cells = <2>;
1003 #io-channel-cells = <1>;
1006 ams_ps: ams_ps@ffa50800 {
1007 compatible = "xlnx,zynqmp-ams-ps";
1008 status = "disabled";
1009 reg = <0x0 0xffa50800 0x0 0x400>;
1012 ams_pl: ams_pl@ffa50c00 {
1013 compatible = "xlnx,zynqmp-ams-pl";
1014 status = "disabled";
1015 reg = <0x0 0xffa50c00 0x0 0x400>;
1019 xlnx_dp: dp@fd4a0000 {
1020 compatible = "xlnx,v-dp";
1021 status = "disabled";
1022 reg = <0x0 0xfd4a0000 0x0 0x1000>;
1023 interrupts = <0 119 4>;
1024 interrupt-parent = <&gic>;
1025 clock-names = "aclk", "aud_clk";
1026 xlnx,dp-version = "v1.2";
1027 xlnx,max-lanes = <2>;
1028 xlnx,max-link-rate = <540000>;
1029 xlnx,max-bpc = <16>;
1031 xlnx,colormetry = "rgb";
1033 xlnx,audio-chan = <2>;
1034 xlnx,dp-sub = <&xlnx_dp_sub>;
1035 xlnx,max-pclock-frequency = <300000>;
1038 xlnx_dp_sub: dp_sub@fd4aa000 {
1039 compatible = "xlnx,dp-sub";
1040 status = "disabled";
1041 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1042 <0x0 0xfd4ab000 0x0 0x1000>,
1043 <0x0 0xfd4ac000 0x0 0x1000>;
1044 reg-names = "blend", "av_buf", "aud";
1045 xlnx,output-fmt = "rgb";
1046 xlnx,vid-fmt = "yuyv";
1047 xlnx,gfx-fmt = "rgb565";
1050 xlnx_dpdma: dma@fd4c0000 {
1051 compatible = "xlnx,dpdma";
1052 status = "disabled";
1053 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1054 interrupts = <0 122 4>;
1055 interrupt-parent = <&gic>;
1056 clock-names = "axi_clk";
1057 power-domains = <&zynqmp_firmware PD_DP>;
1061 compatible = "xlnx,video0";
1064 compatible = "xlnx,video1";
1067 compatible = "xlnx,video2";
1069 dma-graphicschannel {
1070 compatible = "xlnx,graphics";
1073 compatible = "xlnx,audio0";
1076 compatible = "xlnx,audio1";