2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 compatible = "xlnx,zynqmp";
21 compatible = "arm,cortex-a53", "arm,armv8";
23 enable-method = "psci";
24 operating-points-v2 = <&cpu_opp_table>;
26 cpu-idle-states = <&CPU_SLEEP_0>;
30 compatible = "arm,cortex-a53", "arm,armv8";
32 enable-method = "psci";
34 operating-points-v2 = <&cpu_opp_table>;
35 cpu-idle-states = <&CPU_SLEEP_0>;
39 compatible = "arm,cortex-a53", "arm,armv8";
41 enable-method = "psci";
43 operating-points-v2 = <&cpu_opp_table>;
44 cpu-idle-states = <&CPU_SLEEP_0>;
48 compatible = "arm,cortex-a53", "arm,armv8";
50 enable-method = "psci";
52 operating-points-v2 = <&cpu_opp_table>;
53 cpu-idle-states = <&CPU_SLEEP_0>;
57 entry-method = "arm,psci";
59 CPU_SLEEP_0: cpu-sleep-0 {
60 compatible = "arm,idle-state";
61 arm,psci-suspend-param = <0x40000000>;
63 entry-latency-us = <300>;
64 exit-latency-us = <600>;
65 min-residency-us = <10000>;
70 cpu_opp_table: cpu_opp_table {
71 compatible = "operating-points-v2";
74 opp-hz = /bits/ 64 <1199999988>;
75 opp-microvolt = <1000000>;
76 clock-latency-ns = <500000>;
79 opp-hz = /bits/ 64 <599999994>;
80 opp-microvolt = <1000000>;
81 clock-latency-ns = <500000>;
84 opp-hz = /bits/ 64 <399999996>;
85 opp-microvolt = <1000000>;
86 clock-latency-ns = <500000>;
89 opp-hz = /bits/ 64 <299999997>;
90 opp-microvolt = <1000000>;
91 clock-latency-ns = <500000>;
96 compatible = "arm,dcc";
102 compatible = "xlnx,zynqmp-genpd";
105 #power-domain-cells = <0x0>;
110 #power-domain-cells = <0x0>;
115 #power-domain-cells = <0x0>;
120 #power-domain-cells = <0x0>;
125 #power-domain-cells = <0x0>;
130 #power-domain-cells = <0x0>;
135 #power-domain-cells = <0x0>;
140 #power-domain-cells = <0x0>;
145 #power-domain-cells = <0x0>;
150 #power-domain-cells = <0x0>;
155 #power-domain-cells = <0x0>;
160 #power-domain-cells = <0x0>;
165 #power-domain-cells = <0x0>;
170 #power-domain-cells = <0x0>;
175 #power-domain-cells = <0x0>;
180 #power-domain-cells = <0x0>;
185 #power-domain-cells = <0x0>;
190 #power-domain-cells = <0x0>;
195 #power-domain-cells = <0x0>;
200 #power-domain-cells = <0x0>;
205 #power-domain-cells = <0x0>;
210 #power-domain-cells = <0x0>;
215 #power-domain-cells = <0x0>;
220 #power-domain-cells = <0x0>;
225 #power-domain-cells = <0x0>;
230 #power-domain-cells = <0x0>;
235 #power-domain-cells = <0x0>;
240 #power-domain-cells = <0x0>;
245 #power-domain-cells = <0x0>;
246 pd-id = <0x3a 0x14 0x15>;
251 compatible = "arm,armv8-pmuv3";
252 interrupt-parent = <&gic>;
253 interrupts = <0 143 4>,
260 compatible = "arm,psci-0.2";
265 compatible = "xlnx,zynqmp-pm";
267 interrupt-parent = <&gic>;
268 interrupts = <0 35 4>;
272 compatible = "arm,armv8-timer";
273 interrupt-parent = <&gic>;
274 interrupts = <1 13 0xf08>,
281 compatible = "arm,cortex-a53-edac";
284 fpga_full: fpga-full {
285 compatible = "fpga-region";
287 #address-cells = <2>;
292 compatible = "xlnx,zynqmp-nvmem-fw";
293 #address-cells = <1>;
296 soc_revision: soc_revision@0 {
302 compatible = "xlnx,zynqmp-pcap-fpga";
305 rst: reset-controller {
306 compatible = "xlnx,zynqmp-reset";
310 amba_apu: amba_apu@0 {
311 compatible = "simple-bus";
312 #address-cells = <2>;
314 ranges = <0 0 0 0 0xffffffff>;
316 gic: interrupt-controller@f9010000 {
317 compatible = "arm,gic-400", "arm,cortex-a15-gic";
318 #interrupt-cells = <3>;
319 reg = <0x0 0xf9010000 0x10000>,
320 <0x0 0xf9020000 0x20000>,
321 <0x0 0xf9040000 0x20000>,
322 <0x0 0xf9060000 0x20000>;
323 interrupt-controller;
324 interrupt-parent = <&gic>;
325 interrupts = <1 9 0xf04>;
330 compatible = "simple-bus";
332 #address-cells = <2>;
337 compatible = "xlnx,zynq-can-1.0";
339 clock-names = "can_clk", "pclk";
340 reg = <0x0 0xff060000 0x0 0x1000>;
341 interrupts = <0 23 4>;
342 interrupt-parent = <&gic>;
343 tx-fifo-depth = <0x40>;
344 rx-fifo-depth = <0x40>;
345 power-domains = <&pd_can0>;
349 compatible = "xlnx,zynq-can-1.0";
351 clock-names = "can_clk", "pclk";
352 reg = <0x0 0xff070000 0x0 0x1000>;
353 interrupts = <0 24 4>;
354 interrupt-parent = <&gic>;
355 tx-fifo-depth = <0x40>;
356 rx-fifo-depth = <0x40>;
357 power-domains = <&pd_can1>;
361 compatible = "arm,cci-400";
362 reg = <0x0 0xfd6e0000 0x0 0x9000>;
363 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
364 #address-cells = <1>;
368 compatible = "arm,cci-400-pmu,r1";
369 reg = <0x9000 0x5000>;
370 interrupt-parent = <&gic>;
371 interrupts = <0 123 4>,
380 fpd_dma_chan1: dma@fd500000 {
382 compatible = "xlnx,zynqmp-dma-1.0";
383 reg = <0x0 0xfd500000 0x0 0x1000>;
384 interrupt-parent = <&gic>;
385 interrupts = <0 124 4>;
386 clock-names = "clk_main", "clk_apb";
387 xlnx,bus-width = <128>;
388 #stream-id-cells = <1>;
389 iommus = <&smmu 0x14e8>;
390 power-domains = <&pd_gdma>;
393 fpd_dma_chan2: dma@fd510000 {
395 compatible = "xlnx,zynqmp-dma-1.0";
396 reg = <0x0 0xfd510000 0x0 0x1000>;
397 interrupt-parent = <&gic>;
398 interrupts = <0 125 4>;
399 clock-names = "clk_main", "clk_apb";
400 xlnx,bus-width = <128>;
401 #stream-id-cells = <1>;
402 iommus = <&smmu 0x14e9>;
403 power-domains = <&pd_gdma>;
406 fpd_dma_chan3: dma@fd520000 {
408 compatible = "xlnx,zynqmp-dma-1.0";
409 reg = <0x0 0xfd520000 0x0 0x1000>;
410 interrupt-parent = <&gic>;
411 interrupts = <0 126 4>;
412 clock-names = "clk_main", "clk_apb";
413 xlnx,bus-width = <128>;
414 #stream-id-cells = <1>;
415 iommus = <&smmu 0x14ea>;
416 power-domains = <&pd_gdma>;
419 fpd_dma_chan4: dma@fd530000 {
421 compatible = "xlnx,zynqmp-dma-1.0";
422 reg = <0x0 0xfd530000 0x0 0x1000>;
423 interrupt-parent = <&gic>;
424 interrupts = <0 127 4>;
425 clock-names = "clk_main", "clk_apb";
426 xlnx,bus-width = <128>;
427 #stream-id-cells = <1>;
428 iommus = <&smmu 0x14eb>;
429 power-domains = <&pd_gdma>;
432 fpd_dma_chan5: dma@fd540000 {
434 compatible = "xlnx,zynqmp-dma-1.0";
435 reg = <0x0 0xfd540000 0x0 0x1000>;
436 interrupt-parent = <&gic>;
437 interrupts = <0 128 4>;
438 clock-names = "clk_main", "clk_apb";
439 xlnx,bus-width = <128>;
440 #stream-id-cells = <1>;
441 iommus = <&smmu 0x14ec>;
442 power-domains = <&pd_gdma>;
445 fpd_dma_chan6: dma@fd550000 {
447 compatible = "xlnx,zynqmp-dma-1.0";
448 reg = <0x0 0xfd550000 0x0 0x1000>;
449 interrupt-parent = <&gic>;
450 interrupts = <0 129 4>;
451 clock-names = "clk_main", "clk_apb";
452 xlnx,bus-width = <128>;
453 #stream-id-cells = <1>;
454 iommus = <&smmu 0x14ed>;
455 power-domains = <&pd_gdma>;
458 fpd_dma_chan7: dma@fd560000 {
460 compatible = "xlnx,zynqmp-dma-1.0";
461 reg = <0x0 0xfd560000 0x0 0x1000>;
462 interrupt-parent = <&gic>;
463 interrupts = <0 130 4>;
464 clock-names = "clk_main", "clk_apb";
465 xlnx,bus-width = <128>;
466 #stream-id-cells = <1>;
467 iommus = <&smmu 0x14ee>;
468 power-domains = <&pd_gdma>;
471 fpd_dma_chan8: dma@fd570000 {
473 compatible = "xlnx,zynqmp-dma-1.0";
474 reg = <0x0 0xfd570000 0x0 0x1000>;
475 interrupt-parent = <&gic>;
476 interrupts = <0 131 4>;
477 clock-names = "clk_main", "clk_apb";
478 xlnx,bus-width = <128>;
479 #stream-id-cells = <1>;
480 iommus = <&smmu 0x14ef>;
481 power-domains = <&pd_gdma>;
486 compatible = "arm,mali-400", "arm,mali-utgard";
487 reg = <0x0 0xfd4b0000 0x0 0x10000>;
488 interrupt-parent = <&gic>;
489 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
490 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
491 clock-names = "gpu", "gpu_pp0", "gpu_pp1";
492 power-domains = <&pd_gpu>;
495 /* LPDDMA default allows only secured access. inorder to enable
496 * These dma channels, Users should ensure that these dma
497 * Channels are allowed for non secure access.
499 lpd_dma_chan1: dma@ffa80000 {
501 compatible = "xlnx,zynqmp-dma-1.0";
502 clock-names = "clk_main", "clk_apb";
503 reg = <0x0 0xffa80000 0x0 0x1000>;
504 interrupt-parent = <&gic>;
505 interrupts = <0 77 4>;
506 xlnx,bus-width = <64>;
507 #stream-id-cells = <1>;
508 iommus = <&smmu 0x868>;
509 power-domains = <&pd_adma>;
512 lpd_dma_chan2: dma@ffa90000 {
514 compatible = "xlnx,zynqmp-dma-1.0";
515 clock-names = "clk_main", "clk_apb";
516 reg = <0x0 0xffa90000 0x0 0x1000>;
517 interrupt-parent = <&gic>;
518 interrupts = <0 78 4>;
519 xlnx,bus-width = <64>;
520 #stream-id-cells = <1>;
521 iommus = <&smmu 0x869>;
522 power-domains = <&pd_adma>;
525 lpd_dma_chan3: dma@ffaa0000 {
527 compatible = "xlnx,zynqmp-dma-1.0";
528 clock-names = "clk_main", "clk_apb";
529 reg = <0x0 0xffaa0000 0x0 0x1000>;
530 interrupt-parent = <&gic>;
531 interrupts = <0 79 4>;
532 xlnx,bus-width = <64>;
533 #stream-id-cells = <1>;
534 iommus = <&smmu 0x86a>;
535 power-domains = <&pd_adma>;
538 lpd_dma_chan4: dma@ffab0000 {
540 compatible = "xlnx,zynqmp-dma-1.0";
541 clock-names = "clk_main", "clk_apb";
542 reg = <0x0 0xffab0000 0x0 0x1000>;
543 interrupt-parent = <&gic>;
544 interrupts = <0 80 4>;
545 xlnx,bus-width = <64>;
546 #stream-id-cells = <1>;
547 iommus = <&smmu 0x86b>;
548 power-domains = <&pd_adma>;
551 lpd_dma_chan5: dma@ffac0000 {
553 compatible = "xlnx,zynqmp-dma-1.0";
554 clock-names = "clk_main", "clk_apb";
555 reg = <0x0 0xffac0000 0x0 0x1000>;
556 interrupt-parent = <&gic>;
557 interrupts = <0 81 4>;
558 xlnx,bus-width = <64>;
559 #stream-id-cells = <1>;
560 iommus = <&smmu 0x86c>;
561 power-domains = <&pd_adma>;
564 lpd_dma_chan6: dma@ffad0000 {
566 compatible = "xlnx,zynqmp-dma-1.0";
567 clock-names = "clk_main", "clk_apb";
568 reg = <0x0 0xffad0000 0x0 0x1000>;
569 interrupt-parent = <&gic>;
570 interrupts = <0 82 4>;
571 xlnx,bus-width = <64>;
572 #stream-id-cells = <1>;
573 iommus = <&smmu 0x86d>;
574 power-domains = <&pd_adma>;
577 lpd_dma_chan7: dma@ffae0000 {
579 compatible = "xlnx,zynqmp-dma-1.0";
580 clock-names = "clk_main", "clk_apb";
581 reg = <0x0 0xffae0000 0x0 0x1000>;
582 interrupt-parent = <&gic>;
583 interrupts = <0 83 4>;
584 xlnx,bus-width = <64>;
585 #stream-id-cells = <1>;
586 iommus = <&smmu 0x86e>;
587 power-domains = <&pd_adma>;
590 lpd_dma_chan8: dma@ffaf0000 {
592 compatible = "xlnx,zynqmp-dma-1.0";
593 clock-names = "clk_main", "clk_apb";
594 reg = <0x0 0xffaf0000 0x0 0x1000>;
595 interrupt-parent = <&gic>;
596 interrupts = <0 84 4>;
597 xlnx,bus-width = <64>;
598 #stream-id-cells = <1>;
599 iommus = <&smmu 0x86f>;
600 power-domains = <&pd_adma>;
603 mc: memory-controller@fd070000 {
604 compatible = "xlnx,zynqmp-ddrc-2.40a";
605 reg = <0x0 0xfd070000 0x0 0x30000>;
606 interrupt-parent = <&gic>;
607 interrupts = <0 112 4>;
610 nand0: nand@ff100000 {
611 compatible = "arasan,nfc-v3p10";
613 reg = <0x0 0xff100000 0x0 0x1000>;
614 clock-names = "clk_sys", "clk_flash";
615 interrupt-parent = <&gic>;
616 interrupts = <0 14 4>;
617 #address-cells = <2>;
619 #stream-id-cells = <1>;
620 iommus = <&smmu 0x872>;
621 power-domains = <&pd_nand>;
624 gem0: ethernet@ff0b0000 {
625 compatible = "cdns,zynqmp-gem";
627 interrupt-parent = <&gic>;
628 interrupts = <0 57 4>, <0 57 4>;
629 reg = <0x0 0xff0b0000 0x0 0x1000>;
630 clock-names = "pclk", "hclk", "tx_clk";
631 #address-cells = <1>;
633 #stream-id-cells = <1>;
634 iommus = <&smmu 0x874>;
635 power-domains = <&pd_eth0>;
638 gem1: ethernet@ff0c0000 {
639 compatible = "cdns,zynqmp-gem";
641 interrupt-parent = <&gic>;
642 interrupts = <0 59 4>, <0 59 4>;
643 reg = <0x0 0xff0c0000 0x0 0x1000>;
644 clock-names = "pclk", "hclk", "tx_clk";
645 #address-cells = <1>;
647 #stream-id-cells = <1>;
648 iommus = <&smmu 0x875>;
649 power-domains = <&pd_eth1>;
652 gem2: ethernet@ff0d0000 {
653 compatible = "cdns,zynqmp-gem";
655 interrupt-parent = <&gic>;
656 interrupts = <0 61 4>, <0 61 4>;
657 reg = <0x0 0xff0d0000 0x0 0x1000>;
658 clock-names = "pclk", "hclk", "tx_clk";
659 #address-cells = <1>;
661 #stream-id-cells = <1>;
662 iommus = <&smmu 0x876>;
663 power-domains = <&pd_eth2>;
666 gem3: ethernet@ff0e0000 {
667 compatible = "cdns,zynqmp-gem";
669 interrupt-parent = <&gic>;
670 interrupts = <0 63 4>, <0 63 4>;
671 reg = <0x0 0xff0e0000 0x0 0x1000>;
672 clock-names = "pclk", "hclk", "tx_clk";
673 #address-cells = <1>;
675 #stream-id-cells = <1>;
676 iommus = <&smmu 0x877>;
677 power-domains = <&pd_eth3>;
680 gpio: gpio@ff0a0000 {
681 compatible = "xlnx,zynqmp-gpio-1.0";
684 interrupt-parent = <&gic>;
685 interrupts = <0 16 4>;
686 interrupt-controller;
687 #interrupt-cells = <2>;
688 reg = <0x0 0xff0a0000 0x0 0x1000>;
690 power-domains = <&pd_gpio>;
694 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
696 interrupt-parent = <&gic>;
697 interrupts = <0 17 4>;
698 reg = <0x0 0xff020000 0x0 0x1000>;
699 #address-cells = <1>;
701 power-domains = <&pd_i2c0>;
705 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
707 interrupt-parent = <&gic>;
708 interrupts = <0 18 4>;
709 reg = <0x0 0xff030000 0x0 0x1000>;
710 #address-cells = <1>;
712 power-domains = <&pd_i2c1>;
715 ocm: memory-controller@ff960000 {
716 compatible = "xlnx,zynqmp-ocmc-1.0";
717 reg = <0x0 0xff960000 0x0 0x1000>;
718 interrupt-parent = <&gic>;
719 interrupts = <0 10 4>;
722 pcie: pcie@fd0e0000 {
723 compatible = "xlnx,nwl-pcie-2.11";
725 #address-cells = <3>;
727 #interrupt-cells = <1>;
730 interrupt-parent = <&gic>;
731 interrupts = <0 118 4>,
734 <0 115 4>, /* MSI_1 [63...32] */
735 <0 114 4>; /* MSI_0 [31...0] */
736 interrupt-names = "misc","dummy","intx", "msi1", "msi0";
737 msi-parent = <&pcie>;
738 reg = <0x0 0xfd0e0000 0x0 0x1000>,
739 <0x0 0xfd480000 0x0 0x1000>,
740 <0x80 0x00000000 0x0 0x1000000>;
741 reg-names = "breg", "pcireg", "cfg";
742 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
743 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
744 bus-range = <0x00 0xff>;
745 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
746 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
747 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
748 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
749 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
750 power-domains = <&pd_pcie>;
751 pcie_intc: legacy-interrupt-controller {
752 interrupt-controller;
753 #address-cells = <0>;
754 #interrupt-cells = <1>;
759 compatible = "xlnx,zynqmp-qspi-1.0";
761 clock-names = "ref_clk", "pclk";
762 interrupts = <0 15 4>;
763 interrupt-parent = <&gic>;
765 reg = <0x0 0xff0f0000 0x0 0x1000>,
766 <0x0 0xc0000000 0x0 0x8000000>;
767 #address-cells = <1>;
769 #stream-id-cells = <1>;
770 iommus = <&smmu 0x873>;
771 power-domains = <&pd_qspi>;
775 compatible = "xlnx,zynqmp-rtc";
777 reg = <0x0 0xffa60000 0x0 0x100>;
778 interrupt-parent = <&gic>;
779 interrupts = <0 26 4>, <0 27 4>;
780 interrupt-names = "alarm", "sec";
781 calibration = <0x8000>;
784 serdes: zynqmp_phy@fd400000 {
785 compatible = "xlnx,zynqmp-psgtr";
787 reg = <0x0 0xfd400000 0x0 0x40000>,
788 <0x0 0xfd3d0000 0x0 0x1000>,
789 <0x0 0xff5e0000 0x0 0x1000>;
790 reg-names = "serdes", "siou", "lpd";
791 nvmem-cells = <&soc_revision>;
792 nvmem-cell-names = "soc_revision";
793 resets = <&rst 16>, <&rst 59>, <&rst 60>,
794 <&rst 61>, <&rst 62>, <&rst 63>,
795 <&rst 64>, <&rst 3>, <&rst 29>,
796 <&rst 30>, <&rst 31>, <&rst 32>;
797 reset-names = "sata_rst", "usb0_crst", "usb1_crst",
798 "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
799 "usb1_apbrst", "dp_rst", "gem0_rst",
800 "gem1_rst", "gem2_rst", "gem3_rst";
815 sata: ahci@fd0c0000 {
816 compatible = "ceva,ahci-1v84";
818 reg = <0x0 0xfd0c0000 0x0 0x2000>;
819 interrupt-parent = <&gic>;
820 interrupts = <0 133 4>;
821 power-domains = <&pd_sata>;
822 #stream-id-cells = <4>;
823 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
824 <&smmu 0x4c2>, <&smmu 0x4c3>;
828 sdhci0: sdhci@ff160000 {
830 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
832 interrupt-parent = <&gic>;
833 interrupts = <0 48 4>;
834 reg = <0x0 0xff160000 0x0 0x1000>;
835 clock-names = "clk_xin", "clk_ahb";
836 xlnx,device_id = <0>;
837 #stream-id-cells = <1>;
838 iommus = <&smmu 0x870>;
839 power-domains = <&pd_sd0>;
840 nvmem-cells = <&soc_revision>;
841 nvmem-cell-names = "soc_revision";
844 sdhci1: sdhci@ff170000 {
846 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
848 interrupt-parent = <&gic>;
849 interrupts = <0 49 4>;
850 reg = <0x0 0xff170000 0x0 0x1000>;
851 clock-names = "clk_xin", "clk_ahb";
852 xlnx,device_id = <1>;
853 #stream-id-cells = <1>;
854 iommus = <&smmu 0x871>;
855 power-domains = <&pd_sd1>;
856 nvmem-cells = <&soc_revision>;
857 nvmem-cell-names = "soc_revision";
860 pinctrl0: pinctrl@ff180000 {
861 compatible = "xlnx,pinctrl-zynqmp";
863 reg = <0x0 0xff180000 0x0 0x1000>;
866 smmu: smmu@fd800000 {
867 compatible = "arm,mmu-500";
868 reg = <0x0 0xfd800000 0x0 0x20000>;
871 #global-interrupts = <1>;
872 interrupt-parent = <&gic>;
873 interrupts = <0 155 4>,
874 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
875 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
876 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
877 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
881 compatible = "cdns,spi-r1p6";
883 interrupt-parent = <&gic>;
884 interrupts = <0 19 4>;
885 reg = <0x0 0xff040000 0x0 0x1000>;
886 clock-names = "ref_clk", "pclk";
887 #address-cells = <1>;
889 power-domains = <&pd_spi0>;
893 compatible = "cdns,spi-r1p6";
895 interrupt-parent = <&gic>;
896 interrupts = <0 20 4>;
897 reg = <0x0 0xff050000 0x0 0x1000>;
898 clock-names = "ref_clk", "pclk";
899 #address-cells = <1>;
901 power-domains = <&pd_spi1>;
904 ttc0: timer@ff110000 {
905 compatible = "cdns,ttc";
907 interrupt-parent = <&gic>;
908 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
909 reg = <0x0 0xff110000 0x0 0x1000>;
911 power-domains = <&pd_ttc0>;
914 ttc1: timer@ff120000 {
915 compatible = "cdns,ttc";
917 interrupt-parent = <&gic>;
918 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
919 reg = <0x0 0xff120000 0x0 0x1000>;
921 power-domains = <&pd_ttc1>;
924 ttc2: timer@ff130000 {
925 compatible = "cdns,ttc";
927 interrupt-parent = <&gic>;
928 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
929 reg = <0x0 0xff130000 0x0 0x1000>;
931 power-domains = <&pd_ttc2>;
934 ttc3: timer@ff140000 {
935 compatible = "cdns,ttc";
937 interrupt-parent = <&gic>;
938 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
939 reg = <0x0 0xff140000 0x0 0x1000>;
941 power-domains = <&pd_ttc3>;
944 uart0: serial@ff000000 {
946 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
948 interrupt-parent = <&gic>;
949 interrupts = <0 21 4>;
950 reg = <0x0 0xff000000 0x0 0x1000>;
951 clock-names = "uart_clk", "pclk";
952 power-domains = <&pd_uart0>;
955 uart1: serial@ff010000 {
957 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
959 interrupt-parent = <&gic>;
960 interrupts = <0 22 4>;
961 reg = <0x0 0xff010000 0x0 0x1000>;
962 clock-names = "uart_clk", "pclk";
963 power-domains = <&pd_uart1>;
967 #address-cells = <2>;
970 compatible = "xlnx,zynqmp-dwc3";
971 clock-names = "bus_clk", "ref_clk";
972 clocks = <&clk125>, <&clk125>;
973 #stream-id-cells = <1>;
974 iommus = <&smmu 0x860>;
975 power-domains = <&pd_usb0>;
978 dwc3_0: dwc3@fe200000 {
979 compatible = "snps,dwc3";
981 reg = <0x0 0xfe200000 0x0 0x40000>;
982 interrupt-parent = <&gic>;
983 interrupts = <0 65 4>;
984 /* snps,quirk-frame-length-adjustment = <0x20>; */
990 #address-cells = <2>;
993 compatible = "xlnx,zynqmp-dwc3";
994 clock-names = "bus_clk", "ref_clk";
995 clocks = <&clk125>, <&clk125>;
996 #stream-id-cells = <1>;
997 iommus = <&smmu 0x861>;
998 power-domains = <&pd_usb1>;
1001 dwc3_1: dwc3@fe300000 {
1002 compatible = "snps,dwc3";
1003 status = "disabled";
1004 reg = <0x0 0xfe300000 0x0 0x40000>;
1005 interrupt-parent = <&gic>;
1006 interrupts = <0 70 4>;
1007 /* snps,quirk-frame-length-adjustment = <0x20>; */
1012 watchdog0: watchdog@fd4d0000 {
1013 compatible = "cdns,wdt-r1p2";
1014 status = "disabled";
1015 interrupt-parent = <&gic>;
1016 interrupts = <0 113 1>;
1017 reg = <0x0 0xfd4d0000 0x0 0x1000>;
1021 xilinx_ams: ams@ffa50000 {
1022 compatible = "xlnx,zynqmp-ams";
1023 status = "disabled";
1024 interrupt-parent = <&gic>;
1025 interrupts = <0 56 4>;
1026 interrupt-names = "ams-irq";
1027 reg = <0x0 0xffa50000 0x0 0x800>;
1028 reg-names = "ams-base";
1029 #address-cells = <2>;
1031 #io-channel-cells = <1>;
1034 ams_ps: ams_ps@ffa50800 {
1035 compatible = "xlnx,zynqmp-ams-ps";
1036 status = "disabled";
1037 reg = <0x0 0xffa50800 0x0 0x400>;
1040 ams_pl: ams_pl@ffa50c00 {
1041 compatible = "xlnx,zynqmp-ams-pl";
1042 status = "disabled";
1043 reg = <0x0 0xffa50c00 0x0 0x400>;
1047 xilinx_drm: xilinx_drm {
1048 compatible = "xlnx,drm";
1049 status = "disabled";
1050 xlnx,encoder-slave = <&xlnx_dp>;
1051 xlnx,connector-type = "DisplayPort";
1052 xlnx,dp-sub = <&xlnx_dp_sub>;
1054 xlnx,pixel-format = "rgb565";
1056 dmas = <&xlnx_dpdma 3>;
1060 dmas = <&xlnx_dpdma 0>,
1063 dma-names = "dma0", "dma1", "dma2";
1068 xlnx_dp: dp@fd4a0000 {
1069 compatible = "xlnx,v-dp";
1070 status = "disabled";
1071 reg = <0x0 0xfd4a0000 0x0 0x1000>;
1072 interrupts = <0 119 4>;
1073 interrupt-parent = <&gic>;
1074 clock-names = "aclk", "aud_clk";
1075 power-domains = <&pd_dp>;
1076 xlnx,dp-version = "v1.2";
1077 xlnx,max-lanes = <2>;
1078 xlnx,max-link-rate = <540000>;
1079 xlnx,max-bpc = <16>;
1081 xlnx,colormetry = "rgb";
1083 xlnx,audio-chan = <2>;
1084 xlnx,dp-sub = <&xlnx_dp_sub>;
1085 xlnx,max-pclock-frequency = <300000>;
1088 xlnx_dp_snd_card: dp_snd_card {
1089 compatible = "xlnx,dp-snd-card";
1090 status = "disabled";
1091 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
1092 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
1095 xlnx_dp_snd_codec0: dp_snd_codec0 {
1096 compatible = "xlnx,dp-snd-codec";
1097 status = "disabled";
1098 clock-names = "aud_clk";
1101 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
1102 compatible = "xlnx,dp-snd-pcm";
1103 status = "disabled";
1104 dmas = <&xlnx_dpdma 4>;
1108 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1109 compatible = "xlnx,dp-snd-pcm";
1110 status = "disabled";
1111 dmas = <&xlnx_dpdma 5>;
1115 xlnx_dp_sub: dp_sub@fd4aa000 {
1116 compatible = "xlnx,dp-sub";
1117 status = "disabled";
1118 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1119 <0x0 0xfd4ab000 0x0 0x1000>,
1120 <0x0 0xfd4ac000 0x0 0x1000>;
1121 reg-names = "blend", "av_buf", "aud";
1122 xlnx,output-fmt = "rgb";
1123 xlnx,vid-fmt = "yuyv";
1124 xlnx,gfx-fmt = "rgb565";
1125 power-domains = <&pd_dp>;
1128 xlnx_dpdma: dma@fd4c0000 {
1129 compatible = "xlnx,dpdma";
1130 status = "disabled";
1131 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1132 interrupts = <0 122 4>;
1133 interrupt-parent = <&gic>;
1134 clock-names = "axi_clk";
1135 power-domains = <&pd_dp>;
1139 compatible = "xlnx,video0";
1142 compatible = "xlnx,video1";
1145 compatible = "xlnx,video2";
1147 dma-graphicschannel {
1148 compatible = "xlnx,graphics";
1151 compatible = "xlnx,audio0";
1154 compatible = "xlnx,audio1";