arch/arm/dts/zynqmp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP
   4  *
   5  * (C) Copyright 2014 - 2020, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
  16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
  17
  18 / {
  19         compatible = "xlnx,zynqmp";
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu0: cpu@0 {
  28                         compatible = "arm,cortex-a53";
  29                         device_type = "cpu";
  30                         enable-method = "psci";
  31                         operating-points-v2 = <&cpu_opp_table>;
  32                         reg = <0x0>;
  33                         cpu-idle-states = <&CPU_SLEEP_0>;
  34                 };
  35
  36                 cpu1: cpu@1 {
  37                         compatible = "arm,cortex-a53";
  38                         device_type = "cpu";
  39                         enable-method = "psci";
  40                         reg = <0x1>;
  41                         operating-points-v2 = <&cpu_opp_table>;
  42                         cpu-idle-states = <&CPU_SLEEP_0>;
  43                 };
  44
  45                 cpu2: cpu@2 {
  46                         compatible = "arm,cortex-a53";
  47                         device_type = "cpu";
  48                         enable-method = "psci";
  49                         reg = <0x2>;
  50                         operating-points-v2 = <&cpu_opp_table>;
  51                         cpu-idle-states = <&CPU_SLEEP_0>;
  52                 };
  53
  54                 cpu3: cpu@3 {
  55                         compatible = "arm,cortex-a53";
  56                         device_type = "cpu";
  57                         enable-method = "psci";
  58                         reg = <0x3>;
  59                         operating-points-v2 = <&cpu_opp_table>;
  60                         cpu-idle-states = <&CPU_SLEEP_0>;
  61                 };
  62
  63                 idle-states {
  64                         entry-method = "psci";
  65
  66                         CPU_SLEEP_0: cpu-sleep-0 {
  67                                 compatible = "arm,idle-state";
  68                                 arm,psci-suspend-param = <0x40000000>;
  69                                 local-timer-stop;
  70                                 entry-latency-us = <300>;
  71                                 exit-latency-us = <600>;
  72                                 min-residency-us = <10000>;
  73                         };
  74                 };
  75         };
  76
  77         cpu_opp_table: cpu-opp-table {
  78                 compatible = "operating-points-v2";
  79                 opp-shared;
  80                 opp00 {
  81                         opp-hz = /bits/ 64 <1199999988>;
  82                         opp-microvolt = <1000000>;
  83                         clock-latency-ns = <500000>;
  84                 };
  85                 opp01 {
  86                         opp-hz = /bits/ 64 <599999994>;
  87                         opp-microvolt = <1000000>;
  88                         clock-latency-ns = <500000>;
  89                 };
  90                 opp02 {
  91                         opp-hz = /bits/ 64 <399999996>;
  92                         opp-microvolt = <1000000>;
  93                         clock-latency-ns = <500000>;
  94                 };
  95                 opp03 {
  96                         opp-hz = /bits/ 64 <299999997>;
  97                         opp-microvolt = <1000000>;
  98                         clock-latency-ns = <500000>;
  99                 };
 100         };
 101
 102         zynqmp_ipi {
 103                 u-boot,dm-pre-reloc;
 104                 compatible = "xlnx,zynqmp-ipi-mailbox";
 105                 interrupt-parent = <&gic>;
 106                 interrupts = <0 35 4>;
 107                 xlnx,ipi-id = <0>;
 108                 #address-cells = <2>;
 109                 #size-cells = <2>;
 110                 ranges;
 111
 112                 ipi_mailbox_pmu1: mailbox@ff990400 {
 113                         u-boot,dm-pre-reloc;
 114                         reg = <0x0 0xff9905c0 0x0 0x20>,
 115                               <0x0 0xff9905e0 0x0 0x20>,
 116                               <0x0 0xff990e80 0x0 0x20>,
 117                               <0x0 0xff990ea0 0x0 0x20>;
 118                         reg-names = "local_request_region", "local_response_region",
 119                                     "remote_request_region", "remote_response_region";
 120                         #mbox-cells = <1>;
 121                         xlnx,ipi-id = <4>;
 122                 };
 123         };
 124
 125         dcc: dcc {
 126                 compatible = "arm,dcc";
 127                 status = "disabled";
 128                 u-boot,dm-pre-reloc;
 129         };
 130
 131         pmu {
 132                 compatible = "arm,armv8-pmuv3";
 133                 interrupt-parent = <&gic>;
 134                 interrupts = <0 143 4>,
 135                              <0 144 4>,
 136                              <0 145 4>,
 137                              <0 146 4>;
 138         };
 139
 140         psci {
 141                 compatible = "arm,psci-0.2";
 142                 method = "smc";
 143         };
 144
 145         firmware {
 146                 zynqmp_firmware: zynqmp-firmware {
 147                         compatible = "xlnx,zynqmp-firmware";
 148                         method = "smc";
 149                         #power-domain-cells = <0x1>;
 150                         u-boot,dm-pre-reloc;
 151
 152                         zynqmp_pcap: pcap {
 153                                 compatible = "xlnx,zynqmp-pcap-fpga";
 154                                 clock-names = "ref_clk";
 155                         };
 156
 157                         zynqmp_power: zynqmp-power {
 158                                 u-boot,dm-pre-reloc;
 159                                 compatible = "xlnx,zynqmp-power";
 160                                 interrupt-parent = <&gic>;
 161                                 interrupts = <0 35 4>;
 162                                 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
 163                                 mbox-names = "tx", "rx";
 164                         };
 165
 166                         zynqmp_reset: reset-controller {
 167                                 compatible = "xlnx,zynqmp-reset";
 168                                 #reset-cells = <1>;
 169                         };
 170                 };
 171         };
 172
 173         timer {
 174                 compatible = "arm,armv8-timer";
 175                 interrupt-parent = <&gic>;
 176                 interrupts = <1 13 0xf08>,
 177                              <1 14 0xf08>,
 178                              <1 11 0xf08>,
 179                              <1 10 0xf08>;
 180         };
 181
 182         edac {
 183                 compatible = "arm,cortex-a53-edac";
 184         };
 185
 186         fpga_full: fpga-full {
 187                 compatible = "fpga-region";
 188                 fpga-mgr = <&zynqmp_pcap>;
 189                 #address-cells = <2>;
 190                 #size-cells = <2>;
 191                 ranges;
 192         };
 193
 194         nvmem_firmware {
 195                 compatible = "xlnx,zynqmp-nvmem-fw";
 196                 #address-cells = <1>;
 197                 #size-cells = <1>;
 198
 199                 soc_revision: soc_revision@0 {
 200                         reg = <0x0 0x4>;
 201                 };
 202         };
 203
 204         rst: reset-controller {
 205                 compatible = "xlnx,zynqmp-reset";
 206                 #reset-cells = <1>;
 207         };
 208
 209         xlnx_dp_snd_card: dp_snd_card {
 210                 compatible = "xlnx,dp-snd-card";
 211                 status = "disabled";
 212                 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
 213                 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
 214         };
 215
 216         xlnx_dp_snd_codec0: dp_snd_codec0 {
 217                 compatible = "xlnx,dp-snd-codec";
 218                 status = "disabled";
 219                 clock-names = "aud_clk";
 220         };
 221
 222         xlnx_dp_snd_pcm0: dp_snd_pcm0 {
 223                 compatible = "xlnx,dp-snd-pcm";
 224                 status = "disabled";
 225                 dmas = <&xlnx_dpdma 4>;
 226                 dma-names = "tx";
 227         };
 228
 229         xlnx_dp_snd_pcm1: dp_snd_pcm1 {
 230                 compatible = "xlnx,dp-snd-pcm";
 231                 status = "disabled";
 232                 dmas = <&xlnx_dpdma 5>;
 233                 dma-names = "tx";
 234         };
 235
 236         xilinx_drm: xilinx_drm {
 237                 compatible = "xlnx,drm";
 238                 status = "disabled";
 239                 xlnx,encoder-slave = <&xlnx_dp>;
 240                 xlnx,connector-type = "DisplayPort";
 241                 xlnx,dp-sub = <&xlnx_dp_sub>;
 242                 planes {
 243                         xlnx,pixel-format = "rgb565";
 244                         plane0 {
 245                                 dmas = <&xlnx_dpdma 3>;
 246                                 dma-names = "dma0";
 247                         };
 248                         plane1 {
 249                                 dmas = <&xlnx_dpdma 0>,
 250                                         <&xlnx_dpdma 1>,
 251                                         <&xlnx_dpdma 2>;
 252                                 dma-names = "dma0", "dma1", "dma2";
 253                         };
 254                 };
 255         };
 256
 257         amba_apu: amba-apu@0 {
 258                 compatible = "simple-bus";
 259                 #address-cells = <2>;
 260                 #size-cells = <1>;
 261                 ranges = <0 0 0 0 0xffffffff>;
 262
 263                 gic: interrupt-controller@f9010000 {
 264                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
 265                         #interrupt-cells = <3>;
 266                         reg = <0x0 0xf9010000 0x10000>,
 267                               <0x0 0xf9020000 0x20000>,
 268                               <0x0 0xf9040000 0x20000>,
 269                               <0x0 0xf9060000 0x20000>;
 270                         interrupt-controller;
 271                         interrupt-parent = <&gic>;
 272                         interrupts = <1 9 0xf04>;
 273                 };
 274         };
 275
 276         amba: amba {
 277                 compatible = "simple-bus";
 278                 u-boot,dm-pre-reloc;
 279                 #address-cells = <2>;
 280                 #size-cells = <2>;
 281                 ranges;
 282
 283                 can0: can@ff060000 {
 284                         compatible = "xlnx,zynq-can-1.0";
 285                         status = "disabled";
 286                         clock-names = "can_clk", "pclk";
 287                         reg = <0x0 0xff060000 0x0 0x1000>;
 288                         interrupts = <0 23 4>;
 289                         interrupt-parent = <&gic>;
 290                         tx-fifo-depth = <0x40>;
 291                         rx-fifo-depth = <0x40>;
 292                         power-domains = <&zynqmp_firmware PD_CAN_0>;
 293                 };
 294
 295                 can1: can@ff070000 {
 296                         compatible = "xlnx,zynq-can-1.0";
 297                         status = "disabled";
 298                         clock-names = "can_clk", "pclk";
 299                         reg = <0x0 0xff070000 0x0 0x1000>;
 300                         interrupts = <0 24 4>;
 301                         interrupt-parent = <&gic>;
 302                         tx-fifo-depth = <0x40>;
 303                         rx-fifo-depth = <0x40>;
 304                         power-domains = <&zynqmp_firmware PD_CAN_1>;
 305                 };
 306
 307                 cci: cci@fd6e0000 {
 308                         compatible = "arm,cci-400";
 309                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 310                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 311                         #address-cells = <1>;
 312                         #size-cells = <1>;
 313
 314                         pmu@9000 {
 315                                 compatible = "arm,cci-400-pmu,r1";
 316                                 reg = <0x9000 0x5000>;
 317                                 interrupt-parent = <&gic>;
 318                                 interrupts = <0 123 4>,
 319                                              <0 123 4>,
 320                                              <0 123 4>,
 321                                              <0 123 4>,
 322                                              <0 123 4>;
 323                         };
 324                 };
 325
 326                 /* GDMA */
 327                 fpd_dma_chan1: dma@fd500000 {
 328                         status = "disabled";
 329                         compatible = "xlnx,zynqmp-dma-1.0";
 330                         reg = <0x0 0xfd500000 0x0 0x1000>;
 331                         interrupt-parent = <&gic>;
 332                         interrupts = <0 124 4>;
 333                         clock-names = "clk_main", "clk_apb";
 334                         xlnx,bus-width = <128>;
 335                         #stream-id-cells = <1>;
 336                         iommus = <&smmu 0x14e8>;
 337                         power-domains = <&zynqmp_firmware PD_GDMA>;
 338                 };
 339
 340                 fpd_dma_chan2: dma@fd510000 {
 341                         status = "disabled";
 342                         compatible = "xlnx,zynqmp-dma-1.0";
 343                         reg = <0x0 0xfd510000 0x0 0x1000>;
 344                         interrupt-parent = <&gic>;
 345                         interrupts = <0 125 4>;
 346                         clock-names = "clk_main", "clk_apb";
 347                         xlnx,bus-width = <128>;
 348                         #stream-id-cells = <1>;
 349                         iommus = <&smmu 0x14e9>;
 350                         power-domains = <&zynqmp_firmware PD_GDMA>;
 351                 };
 352
 353                 fpd_dma_chan3: dma@fd520000 {
 354                         status = "disabled";
 355                         compatible = "xlnx,zynqmp-dma-1.0";
 356                         reg = <0x0 0xfd520000 0x0 0x1000>;
 357                         interrupt-parent = <&gic>;
 358                         interrupts = <0 126 4>;
 359                         clock-names = "clk_main", "clk_apb";
 360                         xlnx,bus-width = <128>;
 361                         #stream-id-cells = <1>;
 362                         iommus = <&smmu 0x14ea>;
 363                         power-domains = <&zynqmp_firmware PD_GDMA>;
 364                 };
 365
 366                 fpd_dma_chan4: dma@fd530000 {
 367                         status = "disabled";
 368                         compatible = "xlnx,zynqmp-dma-1.0";
 369                         reg = <0x0 0xfd530000 0x0 0x1000>;
 370                         interrupt-parent = <&gic>;
 371                         interrupts = <0 127 4>;
 372                         clock-names = "clk_main", "clk_apb";
 373                         xlnx,bus-width = <128>;
 374                         #stream-id-cells = <1>;
 375                         iommus = <&smmu 0x14eb>;
 376                         power-domains = <&zynqmp_firmware PD_GDMA>;
 377                 };
 378
 379                 fpd_dma_chan5: dma@fd540000 {
 380                         status = "disabled";
 381                         compatible = "xlnx,zynqmp-dma-1.0";
 382                         reg = <0x0 0xfd540000 0x0 0x1000>;
 383                         interrupt-parent = <&gic>;
 384                         interrupts = <0 128 4>;
 385                         clock-names = "clk_main", "clk_apb";
 386                         xlnx,bus-width = <128>;
 387                         #stream-id-cells = <1>;
 388                         iommus = <&smmu 0x14ec>;
 389                         power-domains = <&zynqmp_firmware PD_GDMA>;
 390                 };
 391
 392                 fpd_dma_chan6: dma@fd550000 {
 393                         status = "disabled";
 394                         compatible = "xlnx,zynqmp-dma-1.0";
 395                         reg = <0x0 0xfd550000 0x0 0x1000>;
 396                         interrupt-parent = <&gic>;
 397                         interrupts = <0 129 4>;
 398                         clock-names = "clk_main", "clk_apb";
 399                         xlnx,bus-width = <128>;
 400                         #stream-id-cells = <1>;
 401                         iommus = <&smmu 0x14ed>;
 402                         power-domains = <&zynqmp_firmware PD_GDMA>;
 403                 };
 404
 405                 fpd_dma_chan7: dma@fd560000 {
 406                         status = "disabled";
 407                         compatible = "xlnx,zynqmp-dma-1.0";
 408                         reg = <0x0 0xfd560000 0x0 0x1000>;
 409                         interrupt-parent = <&gic>;
 410                         interrupts = <0 130 4>;
 411                         clock-names = "clk_main", "clk_apb";
 412                         xlnx,bus-width = <128>;
 413                         #stream-id-cells = <1>;
 414                         iommus = <&smmu 0x14ee>;
 415                         power-domains = <&zynqmp_firmware PD_GDMA>;
 416                 };
 417
 418                 fpd_dma_chan8: dma@fd570000 {
 419                         status = "disabled";
 420                         compatible = "xlnx,zynqmp-dma-1.0";
 421                         reg = <0x0 0xfd570000 0x0 0x1000>;
 422                         interrupt-parent = <&gic>;
 423                         interrupts = <0 131 4>;
 424                         clock-names = "clk_main", "clk_apb";
 425                         xlnx,bus-width = <128>;
 426                         #stream-id-cells = <1>;
 427                         iommus = <&smmu 0x14ef>;
 428                         power-domains = <&zynqmp_firmware PD_GDMA>;
 429                 };
 430
 431                 gpu: gpu@fd4b0000 {
 432                         status = "disabled";
 433                         compatible = "arm,mali-400", "arm,mali-utgard";
 434                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 435                         interrupt-parent = <&gic>;
 436                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 437                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 438                         clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 439                         power-domains = <&zynqmp_firmware PD_GPU>;
 440                 };
 441
 442                 /* LPDDMA default allows only secured access. inorder to enable
 443                  * These dma channels, Users should ensure that these dma
 444                  * Channels are allowed for non secure access.
 445                  */
 446                 lpd_dma_chan1: dma@ffa80000 {
 447                         status = "disabled";
 448                         compatible = "xlnx,zynqmp-dma-1.0";
 449                         reg = <0x0 0xffa80000 0x0 0x1000>;
 450                         interrupt-parent = <&gic>;
 451                         interrupts = <0 77 4>;
 452                         clock-names = "clk_main", "clk_apb";
 453                         xlnx,bus-width = <64>;
 454                         #stream-id-cells = <1>;
 455                         iommus = <&smmu 0x868>;
 456                         power-domains = <&zynqmp_firmware PD_ADMA>;
 457                 };
 458
 459                 lpd_dma_chan2: dma@ffa90000 {
 460                         status = "disabled";
 461                         compatible = "xlnx,zynqmp-dma-1.0";
 462                         reg = <0x0 0xffa90000 0x0 0x1000>;
 463                         interrupt-parent = <&gic>;
 464                         interrupts = <0 78 4>;
 465                         clock-names = "clk_main", "clk_apb";
 466                         xlnx,bus-width = <64>;
 467                         #stream-id-cells = <1>;
 468                         iommus = <&smmu 0x869>;
 469                         power-domains = <&zynqmp_firmware PD_ADMA>;
 470                 };
 471
 472                 lpd_dma_chan3: dma@ffaa0000 {
 473                         status = "disabled";
 474                         compatible = "xlnx,zynqmp-dma-1.0";
 475                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 476                         interrupt-parent = <&gic>;
 477                         interrupts = <0 79 4>;
 478                         clock-names = "clk_main", "clk_apb";
 479                         xlnx,bus-width = <64>;
 480                         #stream-id-cells = <1>;
 481                         iommus = <&smmu 0x86a>;
 482                         power-domains = <&zynqmp_firmware PD_ADMA>;
 483                 };
 484
 485                 lpd_dma_chan4: dma@ffab0000 {
 486                         status = "disabled";
 487                         compatible = "xlnx,zynqmp-dma-1.0";
 488                         reg = <0x0 0xffab0000 0x0 0x1000>;
 489                         interrupt-parent = <&gic>;
 490                         interrupts = <0 80 4>;
 491                         clock-names = "clk_main", "clk_apb";
 492                         xlnx,bus-width = <64>;
 493                         #stream-id-cells = <1>;
 494                         iommus = <&smmu 0x86b>;
 495                         power-domains = <&zynqmp_firmware PD_ADMA>;
 496                 };
 497
 498                 lpd_dma_chan5: dma@ffac0000 {
 499                         status = "disabled";
 500                         compatible = "xlnx,zynqmp-dma-1.0";
 501                         reg = <0x0 0xffac0000 0x0 0x1000>;
 502                         interrupt-parent = <&gic>;
 503                         interrupts = <0 81 4>;
 504                         clock-names = "clk_main", "clk_apb";
 505                         xlnx,bus-width = <64>;
 506                         #stream-id-cells = <1>;
 507                         iommus = <&smmu 0x86c>;
 508                         power-domains = <&zynqmp_firmware PD_ADMA>;
 509                 };
 510
 511                 lpd_dma_chan6: dma@ffad0000 {
 512                         status = "disabled";
 513                         compatible = "xlnx,zynqmp-dma-1.0";
 514                         reg = <0x0 0xffad0000 0x0 0x1000>;
 515                         interrupt-parent = <&gic>;
 516                         interrupts = <0 82 4>;
 517                         clock-names = "clk_main", "clk_apb";
 518                         xlnx,bus-width = <64>;
 519                         #stream-id-cells = <1>;
 520                         iommus = <&smmu 0x86d>;
 521                         power-domains = <&zynqmp_firmware PD_ADMA>;
 522                 };
 523
 524                 lpd_dma_chan7: dma@ffae0000 {
 525                         status = "disabled";
 526                         compatible = "xlnx,zynqmp-dma-1.0";
 527                         reg = <0x0 0xffae0000 0x0 0x1000>;
 528                         interrupt-parent = <&gic>;
 529                         interrupts = <0 83 4>;
 530                         clock-names = "clk_main", "clk_apb";
 531                         xlnx,bus-width = <64>;
 532                         #stream-id-cells = <1>;
 533                         iommus = <&smmu 0x86e>;
 534                         power-domains = <&zynqmp_firmware PD_ADMA>;
 535                 };
 536
 537                 lpd_dma_chan8: dma@ffaf0000 {
 538                         status = "disabled";
 539                         compatible = "xlnx,zynqmp-dma-1.0";
 540                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 541                         interrupt-parent = <&gic>;
 542                         interrupts = <0 84 4>;
 543                         clock-names = "clk_main", "clk_apb";
 544                         xlnx,bus-width = <64>;
 545                         #stream-id-cells = <1>;
 546                         iommus = <&smmu 0x86f>;
 547                         power-domains = <&zynqmp_firmware PD_ADMA>;
 548                 };
 549
 550                 mc: memory-controller@fd070000 {
 551                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 552                         reg = <0x0 0xfd070000 0x0 0x30000>;
 553                         interrupt-parent = <&gic>;
 554                         interrupts = <0 112 4>;
 555                 };
 556
 557                 nand0: nand@ff100000 {
 558                         compatible = "arasan,nfc-v3p10";
 559                         status = "disabled";
 560                         reg = <0x0 0xff100000 0x0 0x1000>;
 561                         clock-names = "clk_sys", "clk_flash";
 562                         interrupt-parent = <&gic>;
 563                         interrupts = <0 14 4>;
 564                         #address-cells = <1>;
 565                         #size-cells = <0>;
 566                         #stream-id-cells = <1>;
 567                         iommus = <&smmu 0x872>;
 568                         power-domains = <&zynqmp_firmware PD_NAND>;
 569                 };
 570
 571                 gem0: ethernet@ff0b0000 {
 572                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 573                         status = "disabled";
 574                         interrupt-parent = <&gic>;
 575                         interrupts = <0 57 4>, <0 57 4>;
 576                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 577                         clock-names = "pclk", "hclk", "tx_clk";
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                         #stream-id-cells = <1>;
 581                         iommus = <&smmu 0x874>;
 582                         power-domains = <&zynqmp_firmware PD_ETH_0>;
 583                 };
 584
 585                 gem1: ethernet@ff0c0000 {
 586                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 587                         status = "disabled";
 588                         interrupt-parent = <&gic>;
 589                         interrupts = <0 59 4>, <0 59 4>;
 590                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 591                         clock-names = "pclk", "hclk", "tx_clk";
 592                         #address-cells = <1>;
 593                         #size-cells = <0>;
 594                         #stream-id-cells = <1>;
 595                         iommus = <&smmu 0x875>;
 596                         power-domains = <&zynqmp_firmware PD_ETH_1>;
 597                 };
 598
 599                 gem2: ethernet@ff0d0000 {
 600                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 601                         status = "disabled";
 602                         interrupt-parent = <&gic>;
 603                         interrupts = <0 61 4>, <0 61 4>;
 604                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 605                         clock-names = "pclk", "hclk", "tx_clk";
 606                         #address-cells = <1>;
 607                         #size-cells = <0>;
 608                         #stream-id-cells = <1>;
 609                         iommus = <&smmu 0x876>;
 610                         power-domains = <&zynqmp_firmware PD_ETH_2>;
 611                 };
 612
 613                 gem3: ethernet@ff0e0000 {
 614                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 615                         status = "disabled";
 616                         interrupt-parent = <&gic>;
 617                         interrupts = <0 63 4>, <0 63 4>;
 618                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 619                         clock-names = "pclk", "hclk", "tx_clk";
 620                         #address-cells = <1>;
 621                         #size-cells = <0>;
 622                         #stream-id-cells = <1>;
 623                         iommus = <&smmu 0x877>;
 624                         power-domains = <&zynqmp_firmware PD_ETH_3>;
 625                 };
 626
 627                 gpio: gpio@ff0a0000 {
 628                         compatible = "xlnx,zynqmp-gpio-1.0";
 629                         status = "disabled";
 630                         #gpio-cells = <0x2>;
 631                         gpio-controller;
 632                         interrupt-parent = <&gic>;
 633                         interrupts = <0 16 4>;
 634                         interrupt-controller;
 635                         #interrupt-cells = <2>;
 636                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 637                         power-domains = <&zynqmp_firmware PD_GPIO>;
 638                 };
 639
 640                 i2c0: i2c@ff020000 {
 641                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 642                         status = "disabled";
 643                         interrupt-parent = <&gic>;
 644                         interrupts = <0 17 4>;
 645                         reg = <0x0 0xff020000 0x0 0x1000>;
 646                         #address-cells = <1>;
 647                         #size-cells = <0>;
 648                         power-domains = <&zynqmp_firmware PD_I2C_0>;
 649                 };
 650
 651                 i2c1: i2c@ff030000 {
 652                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 653                         status = "disabled";
 654                         interrupt-parent = <&gic>;
 655                         interrupts = <0 18 4>;
 656                         reg = <0x0 0xff030000 0x0 0x1000>;
 657                         #address-cells = <1>;
 658                         #size-cells = <0>;
 659                         power-domains = <&zynqmp_firmware PD_I2C_1>;
 660                 };
 661
 662                 ocm: memory-controller@ff960000 {
 663                         compatible = "xlnx,zynqmp-ocmc-1.0";
 664                         reg = <0x0 0xff960000 0x0 0x1000>;
 665                         interrupt-parent = <&gic>;
 666                         interrupts = <0 10 4>;
 667                 };
 668
 669                 pcie: pcie@fd0e0000 {
 670                         compatible = "xlnx,nwl-pcie-2.11";
 671                         status = "disabled";
 672                         #address-cells = <3>;
 673                         #size-cells = <2>;
 674                         #interrupt-cells = <1>;
 675                         msi-controller;
 676                         device_type = "pci";
 677                         interrupt-parent = <&gic>;
 678                         interrupts = <0 118 4>,
 679                                      <0 117 4>,
 680                                      <0 116 4>,
 681                                      <0 115 4>, /* MSI_1 [63...32] */
 682                                      <0 114 4>; /* MSI_0 [31...0] */
 683                         interrupt-names = "misc", "dummy", "intx",
 684                                           "msi1", "msi0";
 685                         msi-parent = <&pcie>;
 686                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 687                               <0x0 0xfd480000 0x0 0x1000>,
 688                               <0x80 0x00000000 0x0 0x1000000>;
 689                         reg-names = "breg", "pcireg", "cfg";
 690                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 691                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 692                         bus-range = <0x00 0xff>;
 693                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 694                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 695                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 696                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 697                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 698                         power-domains = <&zynqmp_firmware PD_PCIE>;
 699                         pcie_intc: legacy-interrupt-controller {
 700                                 interrupt-controller;
 701                                 #address-cells = <0>;
 702                                 #interrupt-cells = <1>;
 703                         };
 704                 };
 705
 706                 qspi: spi@ff0f0000 {
 707                         u-boot,dm-pre-reloc;
 708                         compatible = "xlnx,zynqmp-qspi-1.0";
 709                         status = "disabled";
 710                         clock-names = "ref_clk", "pclk";
 711                         interrupts = <0 15 4>;
 712                         interrupt-parent = <&gic>;
 713                         num-cs = <1>;
 714                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 715                               <0x0 0xc0000000 0x0 0x8000000>;
 716                         #address-cells = <1>;
 717                         #size-cells = <0>;
 718                         #stream-id-cells = <1>;
 719                         iommus = <&smmu 0x873>;
 720                         power-domains = <&zynqmp_firmware PD_QSPI>;
 721                 };
 722
 723                 rtc: rtc@ffa60000 {
 724                         compatible = "xlnx,zynqmp-rtc";
 725                         status = "disabled";
 726                         reg = <0x0 0xffa60000 0x0 0x100>;
 727                         interrupt-parent = <&gic>;
 728                         interrupts = <0 26 4>, <0 27 4>;
 729                         interrupt-names = "alarm", "sec";
 730                         calibration = <0x8000>;
 731                 };
 732
 733                 serdes: zynqmp_phy@fd400000 {
 734                         compatible = "xlnx,zynqmp-psgtr";
 735                         status = "disabled";
 736                         reg = <0x0 0xfd400000 0x0 0x40000>,
 737                               <0x0 0xfd3d0000 0x0 0x1000>,
 738                               <0x0 0xff5e0000 0x0 0x1000>;
 739                         reg-names = "serdes", "siou", "lpd";
 740                         nvmem-cells = <&soc_revision>;
 741                         nvmem-cell-names = "soc_revision";
 742                         resets = <&zynqmp_reset ZYNQMP_RESET_SATA>,
 743                                  <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
 744                                  <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
 745                                  <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
 746                                  <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
 747                                  <&zynqmp_reset ZYNQMP_RESET_USB0_APB>,
 748                                  <&zynqmp_reset ZYNQMP_RESET_USB1_APB>,
 749                                  <&zynqmp_reset ZYNQMP_RESET_DP>,
 750                                  <&zynqmp_reset ZYNQMP_RESET_GEM0>,
 751                                  <&zynqmp_reset ZYNQMP_RESET_GEM1>,
 752                                  <&zynqmp_reset ZYNQMP_RESET_GEM2>,
 753                                  <&zynqmp_reset ZYNQMP_RESET_GEM3>;
 754                         reset-names = "sata_rst", "usb0_crst", "usb1_crst",
 755                                       "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
 756                                       "usb1_apbrst", "dp_rst", "gem0_rst",
 757                                       "gem1_rst", "gem2_rst", "gem3_rst";
 758                         lane0: lane0 {
 759                                 #phy-cells = <4>;
 760                         };
 761                         lane1: lane1 {
 762                                 #phy-cells = <4>;
 763                         };
 764                         lane2: lane2 {
 765                                 #phy-cells = <4>;
 766                         };
 767                         lane3: lane3 {
 768                                 #phy-cells = <4>;
 769                         };
 770                 };
 771
 772                 sata: ahci@fd0c0000 {
 773                         compatible = "ceva,ahci-1v84";
 774                         status = "disabled";
 775                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 776                         interrupt-parent = <&gic>;
 777                         interrupts = <0 133 4>;
 778                         power-domains = <&zynqmp_firmware PD_SATA>;
 779                         #stream-id-cells = <4>;
 780                         iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 781                                  <&smmu 0x4c2>, <&smmu 0x4c3>;
 782                         /* dma-coherent; */
 783                 };
 784
 785                 sdhci0: mmc@ff160000 {
 786                         u-boot,dm-pre-reloc;
 787                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 788                         status = "disabled";
 789                         interrupt-parent = <&gic>;
 790                         interrupts = <0 48 4>;
 791                         reg = <0x0 0xff160000 0x0 0x1000>;
 792                         clock-names = "clk_xin", "clk_ahb";
 793                         xlnx,device_id = <0>;
 794                         #stream-id-cells = <1>;
 795                         iommus = <&smmu 0x870>;
 796                         power-domains = <&zynqmp_firmware PD_SD_0>;
 797                         nvmem-cells = <&soc_revision>;
 798                         nvmem-cell-names = "soc_revision";
 799                 };
 800
 801                 sdhci1: mmc@ff170000 {
 802                         u-boot,dm-pre-reloc;
 803                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 804                         status = "disabled";
 805                         interrupt-parent = <&gic>;
 806                         interrupts = <0 49 4>;
 807                         reg = <0x0 0xff170000 0x0 0x1000>;
 808                         clock-names = "clk_xin", "clk_ahb";
 809                         xlnx,device_id = <1>;
 810                         #stream-id-cells = <1>;
 811                         iommus = <&smmu 0x871>;
 812                         power-domains = <&zynqmp_firmware PD_SD_1>;
 813                         nvmem-cells = <&soc_revision>;
 814                         nvmem-cell-names = "soc_revision";
 815                 };
 816
 817                 pinctrl0: pinctrl@ff180000 {
 818                         compatible = "xlnx,pinctrl-zynqmp";
 819                         status = "disabled";
 820                         reg = <0x0 0xff180000 0x0 0x1000>;
 821                 };
 822
 823                 smmu: smmu@fd800000 {
 824                         compatible = "arm,mmu-500";
 825                         reg = <0x0 0xfd800000 0x0 0x20000>;
 826                         #iommu-cells = <1>;
 827                         status = "disabled";
 828                         #global-interrupts = <1>;
 829                         interrupt-parent = <&gic>;
 830                         interrupts = <0 155 4>,
 831                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 832                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 833                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 834                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 835                 };
 836
 837                 spi0: spi@ff040000 {
 838                         compatible = "cdns,spi-r1p6";
 839                         status = "disabled";
 840                         interrupt-parent = <&gic>;
 841                         interrupts = <0 19 4>;
 842                         reg = <0x0 0xff040000 0x0 0x1000>;
 843                         clock-names = "ref_clk", "pclk";
 844                         #address-cells = <1>;
 845                         #size-cells = <0>;
 846                         power-domains = <&zynqmp_firmware PD_SPI_0>;
 847                 };
 848
 849                 spi1: spi@ff050000 {
 850                         compatible = "cdns,spi-r1p6";
 851                         status = "disabled";
 852                         interrupt-parent = <&gic>;
 853                         interrupts = <0 20 4>;
 854                         reg = <0x0 0xff050000 0x0 0x1000>;
 855                         clock-names = "ref_clk", "pclk";
 856                         #address-cells = <1>;
 857                         #size-cells = <0>;
 858                         power-domains = <&zynqmp_firmware PD_SPI_1>;
 859                 };
 860
 861                 ttc0: timer@ff110000 {
 862                         compatible = "cdns,ttc";
 863                         status = "disabled";
 864                         interrupt-parent = <&gic>;
 865                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 866                         reg = <0x0 0xff110000 0x0 0x1000>;
 867                         timer-width = <32>;
 868                         power-domains = <&zynqmp_firmware PD_TTC_0>;
 869                 };
 870
 871                 ttc1: timer@ff120000 {
 872                         compatible = "cdns,ttc";
 873                         status = "disabled";
 874                         interrupt-parent = <&gic>;
 875                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 876                         reg = <0x0 0xff120000 0x0 0x1000>;
 877                         timer-width = <32>;
 878                         power-domains = <&zynqmp_firmware PD_TTC_1>;
 879                 };
 880
 881                 ttc2: timer@ff130000 {
 882                         compatible = "cdns,ttc";
 883                         status = "disabled";
 884                         interrupt-parent = <&gic>;
 885                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 886                         reg = <0x0 0xff130000 0x0 0x1000>;
 887                         timer-width = <32>;
 888                         power-domains = <&zynqmp_firmware PD_TTC_2>;
 889                 };
 890
 891                 ttc3: timer@ff140000 {
 892                         compatible = "cdns,ttc";
 893                         status = "disabled";
 894                         interrupt-parent = <&gic>;
 895                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 896                         reg = <0x0 0xff140000 0x0 0x1000>;
 897                         timer-width = <32>;
 898                         power-domains = <&zynqmp_firmware PD_TTC_3>;
 899                 };
 900
 901                 uart0: serial@ff000000 {
 902                         u-boot,dm-pre-reloc;
 903                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 904                         status = "disabled";
 905                         interrupt-parent = <&gic>;
 906                         interrupts = <0 21 4>;
 907                         reg = <0x0 0xff000000 0x0 0x1000>;
 908                         clock-names = "uart_clk", "pclk";
 909                         power-domains = <&zynqmp_firmware PD_UART_0>;
 910                 };
 911
 912                 uart1: serial@ff010000 {
 913                         u-boot,dm-pre-reloc;
 914                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 915                         status = "disabled";
 916                         interrupt-parent = <&gic>;
 917                         interrupts = <0 22 4>;
 918                         reg = <0x0 0xff010000 0x0 0x1000>;
 919                         clock-names = "uart_clk", "pclk";
 920                         power-domains = <&zynqmp_firmware PD_UART_1>;
 921                 };
 922
 923                 usb0: usb0@ff9d0000 {
 924                         #address-cells = <2>;
 925                         #size-cells = <2>;
 926                         status = "disabled";
 927                         compatible = "xlnx,zynqmp-dwc3";
 928                         reg = <0x0 0xff9d0000 0x0 0x100>;
 929                         clock-names = "bus_clk", "ref_clk";
 930                         power-domains = <&zynqmp_firmware PD_USB_0>;
 931                         ranges;
 932                         nvmem-cells = <&soc_revision>;
 933                         nvmem-cell-names = "soc_revision";
 934
 935                         dwc3_0: dwc3@fe200000 {
 936                                 compatible = "snps,dwc3";
 937                                 status = "disabled";
 938                                 reg = <0x0 0xfe200000 0x0 0x40000>;
 939                                 interrupt-parent = <&gic>;
 940                                 interrupts = <0 65 4>, <0 69 4>;
 941                                 #stream-id-cells = <1>;
 942                                 iommus = <&smmu 0x860>;
 943                                 snps,quirk-frame-length-adjustment = <0x20>;
 944                                 snps,refclk_fladj;
 945                                 /* dma-coherent; */
 946                         };
 947                 };
 948
 949                 usb1: usb1@ff9e0000 {
 950                         #address-cells = <2>;
 951                         #size-cells = <2>;
 952                         status = "disabled";
 953                         compatible = "xlnx,zynqmp-dwc3";
 954                         reg = <0x0 0xff9e0000 0x0 0x100>;
 955                         clock-names = "bus_clk", "ref_clk";
 956                         power-domains = <&zynqmp_firmware PD_USB_1>;
 957                         ranges;
 958                         nvmem-cells = <&soc_revision>;
 959                         nvmem-cell-names = "soc_revision";
 960
 961                         dwc3_1: dwc3@fe300000 {
 962                                 compatible = "snps,dwc3";
 963                                 status = "disabled";
 964                                 reg = <0x0 0xfe300000 0x0 0x40000>;
 965                                 interrupt-parent = <&gic>;
 966                                 interrupts = <0 70 4>, <0 74 4>;
 967                                 #stream-id-cells = <1>;
 968                                 iommus = <&smmu 0x861>;
 969                                 snps,quirk-frame-length-adjustment = <0x20>;
 970                                 snps,refclk_fladj;
 971                                 /* dma-coherent; */
 972                         };
 973                 };
 974
 975                 watchdog0: watchdog@fd4d0000 {
 976                         compatible = "cdns,wdt-r1p2";
 977                         status = "disabled";
 978                         interrupt-parent = <&gic>;
 979                         interrupts = <0 113 1>;
 980                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
 981                         timeout-sec = <60>;
 982                         reset-on-timeout;
 983                 };
 984
 985                 lpd_watchdog: watchdog@ff150000 {
 986                         compatible = "cdns,wdt-r1p2";
 987                         status = "disabled";
 988                         interrupt-parent = <&gic>;
 989                         interrupts = <0 52 1>;
 990                         reg = <0x0 0xff150000 0x0 0x1000>;
 991                         timeout-sec = <10>;
 992                 };
 993
 994                 xilinx_ams: ams@ffa50000 {
 995                         compatible = "xlnx,zynqmp-ams";
 996                         status = "disabled";
 997                         interrupt-parent = <&gic>;
 998                         interrupts = <0 56 4>;
 999                         interrupt-names = "ams-irq";
1000                         reg = <0x0 0xffa50000 0x0 0x800>;
1001                         reg-names = "ams-base";
1002                         #address-cells = <2>;
1003                         #size-cells = <2>;
1004                         #io-channel-cells = <1>;
1005                         ranges;
1006
1007                         ams_ps: ams_ps@ffa50800 {
1008                                 compatible = "xlnx,zynqmp-ams-ps";
1009                                 status = "disabled";
1010                                 reg = <0x0 0xffa50800 0x0 0x400>;
1011                         };
1012
1013                         ams_pl: ams_pl@ffa50c00 {
1014                                 compatible = "xlnx,zynqmp-ams-pl";
1015                                 status = "disabled";
1016                                 reg = <0x0 0xffa50c00 0x0 0x400>;
1017                         };
1018                 };
1019
1020                 xlnx_dp: dp@fd4a0000 {
1021                         compatible = "xlnx,v-dp";
1022                         status = "disabled";
1023                         reg = <0x0 0xfd4a0000 0x0 0x1000>;
1024                         interrupts = <0 119 4>;
1025                         interrupt-parent = <&gic>;
1026                         clock-names = "aclk", "aud_clk";
1027                         xlnx,dp-version = "v1.2";
1028                         xlnx,max-lanes = <2>;
1029                         xlnx,max-link-rate = <540000>;
1030                         xlnx,max-bpc = <16>;
1031                         xlnx,enable-ycrcb;
1032                         xlnx,colormetry = "rgb";
1033                         xlnx,bpc = <8>;
1034                         xlnx,audio-chan = <2>;
1035                         xlnx,dp-sub = <&xlnx_dp_sub>;
1036                         xlnx,max-pclock-frequency = <300000>;
1037                 };
1038
1039                 xlnx_dp_sub: dp_sub@fd4aa000 {
1040                         compatible = "xlnx,dp-sub";
1041                         status = "disabled";
1042                         reg = <0x0 0xfd4aa000 0x0 0x1000>,
1043                               <0x0 0xfd4ab000 0x0 0x1000>,
1044                               <0x0 0xfd4ac000 0x0 0x1000>;
1045                         reg-names = "blend", "av_buf", "aud";
1046                         xlnx,output-fmt = "rgb";
1047                         xlnx,vid-fmt = "yuyv";
1048                         xlnx,gfx-fmt = "rgb565";
1049                 };
1050
1051                 xlnx_dpdma: dma@fd4c0000 {
1052                         compatible = "xlnx,dpdma";
1053                         status = "disabled";
1054                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
1055                         interrupts = <0 122 4>;
1056                         interrupt-parent = <&gic>;
1057                         clock-names = "axi_clk";
1058                         power-domains = <&zynqmp_firmware PD_DP>;
1059                         dma-channels = <6>;
1060                         #dma-cells = <1>;
1061                         dma-video0channel {
1062                                 compatible = "xlnx,video0";
1063                         };
1064                         dma-video1channel {
1065                                 compatible = "xlnx,video1";
1066                         };
1067                         dma-video2channel {
1068                                 compatible = "xlnx,video2";
1069                         };
1070                         dma-graphicschannel {
1071                                 compatible = "xlnx,graphics";
1072                         };
1073                         dma-audio0channel {
1074                                 compatible = "xlnx,audio0";
1075                         };
1076                         dma-audio1channel {
1077                                 compatible = "xlnx,audio1";
1078                         };
1079                 };
1080         };
1081 };