arch/arm/dts/zynqmp.dtsi

   1 /*
   2  * dts file for Xilinx ZynqMP
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 / {
  12         compatible = "xlnx,zynqmp";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@0 {
  21                         compatible = "arm,cortex-a53", "arm,armv8";
  22                         device_type = "cpu";
  23                         enable-method = "psci";
  24                         operating-points-v2 = <&cpu_opp_table>;
  25                         reg = <0x0>;
  26                         cpu-idle-states = <&CPU_SLEEP_0>;
  27                 };
  28
  29                 cpu1: cpu@1 {
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         device_type = "cpu";
  32                         enable-method = "psci";
  33                         reg = <0x1>;
  34                         operating-points-v2 = <&cpu_opp_table>;
  35                         cpu-idle-states = <&CPU_SLEEP_0>;
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         device_type = "cpu";
  41                         enable-method = "psci";
  42                         reg = <0x2>;
  43                         operating-points-v2 = <&cpu_opp_table>;
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                 };
  46
  47                 cpu3: cpu@3 {
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         device_type = "cpu";
  50                         enable-method = "psci";
  51                         reg = <0x3>;
  52                         operating-points-v2 = <&cpu_opp_table>;
  53                         cpu-idle-states = <&CPU_SLEEP_0>;
  54                 };
  55
  56                 idle-states {
  57                         entry-method = "arm,psci";
  58
  59                         CPU_SLEEP_0: cpu-sleep-0 {
  60                                 compatible = "arm,idle-state";
  61                                 arm,psci-suspend-param = <0x40000000>;
  62                                 local-timer-stop;
  63                                 entry-latency-us = <300>;
  64                                 exit-latency-us = <600>;
  65                                 min-residency-us = <10000>;
  66                         };
  67                 };
  68         };
  69
  70         cpu_opp_table: cpu_opp_table {
  71                 compatible = "operating-points-v2";
  72                 opp-shared;
  73                 opp00 {
  74                         opp-hz = /bits/ 64 <1199999988>;
  75                         opp-microvolt = <1000000>;
  76                         clock-latency-ns = <500000>;
  77                 };
  78                 opp01 {
  79                         opp-hz = /bits/ 64 <599999994>;
  80                         opp-microvolt = <1000000>;
  81                         clock-latency-ns = <500000>;
  82                 };
  83                 opp02 {
  84                         opp-hz = /bits/ 64 <399999996>;
  85                         opp-microvolt = <1000000>;
  86                         clock-latency-ns = <500000>;
  87                 };
  88                 opp03 {
  89                         opp-hz = /bits/ 64 <299999997>;
  90                         opp-microvolt = <1000000>;
  91                         clock-latency-ns = <500000>;
  92                 };
  93         };
  94
  95         dcc: dcc {
  96                 compatible = "arm,dcc";
  97                 status = "disabled";
  98                 u-boot,dm-pre-reloc;
  99         };
 100
 101         power-domains {
 102                 compatible = "xlnx,zynqmp-genpd";
 103
 104                 pd_usb0: pd-usb0 {
 105                         #power-domain-cells = <0x0>;
 106                         pd-id = <0x16>;
 107                 };
 108
 109                 pd_usb1: pd-usb1 {
 110                         #power-domain-cells = <0x0>;
 111                         pd-id = <0x17>;
 112                 };
 113
 114                 pd_sata: pd-sata {
 115                         #power-domain-cells = <0x0>;
 116                         pd-id = <0x1c>;
 117                 };
 118
 119                 pd_spi0: pd-spi0 {
 120                         #power-domain-cells = <0x0>;
 121                         pd-id = <0x23>;
 122                 };
 123
 124                 pd_spi1: pd-spi1 {
 125                         #power-domain-cells = <0x0>;
 126                         pd-id = <0x24>;
 127                 };
 128
 129                 pd_uart0: pd-uart0 {
 130                         #power-domain-cells = <0x0>;
 131                         pd-id = <0x21>;
 132                 };
 133
 134                 pd_uart1: pd-uart1 {
 135                         #power-domain-cells = <0x0>;
 136                         pd-id = <0x22>;
 137                 };
 138
 139                 pd_eth0: pd-eth0 {
 140                         #power-domain-cells = <0x0>;
 141                         pd-id = <0x1d>;
 142                 };
 143
 144                 pd_eth1: pd-eth1 {
 145                         #power-domain-cells = <0x0>;
 146                         pd-id = <0x1e>;
 147                 };
 148
 149                 pd_eth2: pd-eth2 {
 150                         #power-domain-cells = <0x0>;
 151                         pd-id = <0x1f>;
 152                 };
 153
 154                 pd_eth3: pd-eth3 {
 155                         #power-domain-cells = <0x0>;
 156                         pd-id = <0x20>;
 157                 };
 158
 159                 pd_i2c0: pd-i2c0 {
 160                         #power-domain-cells = <0x0>;
 161                         pd-id = <0x25>;
 162                 };
 163
 164                 pd_i2c1: pd-i2c1 {
 165                         #power-domain-cells = <0x0>;
 166                         pd-id = <0x26>;
 167                 };
 168
 169                 pd_dp: pd-dp {
 170                         #power-domain-cells = <0x0>;
 171                         pd-id = <0x29>;
 172                 };
 173
 174                 pd_gdma: pd-gdma {
 175                         #power-domain-cells = <0x0>;
 176                         pd-id = <0x2a>;
 177                 };
 178
 179                 pd_adma: pd-adma {
 180                         #power-domain-cells = <0x0>;
 181                         pd-id = <0x2b>;
 182                 };
 183
 184                 pd_ttc0: pd-ttc0 {
 185                         #power-domain-cells = <0x0>;
 186                         pd-id = <0x18>;
 187                 };
 188
 189                 pd_ttc1: pd-ttc1 {
 190                         #power-domain-cells = <0x0>;
 191                         pd-id = <0x19>;
 192                 };
 193
 194                 pd_ttc2: pd-ttc2 {
 195                         #power-domain-cells = <0x0>;
 196                         pd-id = <0x1a>;
 197                 };
 198
 199                 pd_ttc3: pd-ttc3 {
 200                         #power-domain-cells = <0x0>;
 201                         pd-id = <0x1b>;
 202                 };
 203
 204                 pd_sd0: pd-sd0 {
 205                         #power-domain-cells = <0x0>;
 206                         pd-id = <0x27>;
 207                 };
 208
 209                 pd_sd1: pd-sd1 {
 210                         #power-domain-cells = <0x0>;
 211                         pd-id = <0x28>;
 212                 };
 213
 214                 pd_nand: pd-nand {
 215                         #power-domain-cells = <0x0>;
 216                         pd-id = <0x2c>;
 217                 };
 218
 219                 pd_qspi: pd-qspi {
 220                         #power-domain-cells = <0x0>;
 221                         pd-id = <0x2d>;
 222                 };
 223
 224                 pd_gpio: pd-gpio {
 225                         #power-domain-cells = <0x0>;
 226                         pd-id = <0x2e>;
 227                 };
 228
 229                 pd_can0: pd-can0 {
 230                         #power-domain-cells = <0x0>;
 231                         pd-id = <0x2f>;
 232                 };
 233
 234                 pd_can1: pd-can1 {
 235                         #power-domain-cells = <0x0>;
 236                         pd-id = <0x30>;
 237                 };
 238
 239                 pd_pcie: pd-pcie {
 240                         #power-domain-cells = <0x0>;
 241                         pd-id = <0x3b>;
 242                 };
 243
 244                 pd_gpu: pd-gpu {
 245                         #power-domain-cells = <0x0>;
 246                         pd-id = <0x3a 0x14 0x15>;
 247                 };
 248         };
 249
 250         pmu {
 251                 compatible = "arm,armv8-pmuv3";
 252                 interrupt-parent = <&gic>;
 253                 interrupts = <0 143 4>,
 254                              <0 144 4>,
 255                              <0 145 4>,
 256                              <0 146 4>;
 257         };
 258
 259         psci {
 260                 compatible = "arm,psci-0.2";
 261                 method = "smc";
 262         };
 263
 264         firmware {
 265                 compatible = "xlnx,zynqmp-pm";
 266                 method = "smc";
 267                 interrupt-parent = <&gic>;
 268                 interrupts = <0 35 4>;
 269         };
 270
 271         timer {
 272                 compatible = "arm,armv8-timer";
 273                 interrupt-parent = <&gic>;
 274                 interrupts = <1 13 0xf08>,
 275                              <1 14 0xf08>,
 276                              <1 11 0xf08>,
 277                              <1 10 0xf08>;
 278         };
 279
 280         edac {
 281                 compatible = "arm,cortex-a53-edac";
 282         };
 283
 284         fpga_full: fpga-full {
 285                 compatible = "fpga-region";
 286                 fpga-mgr = <&pcap>;
 287                 #address-cells = <2>;
 288                 #size-cells = <2>;
 289         };
 290
 291         nvmem_firmware {
 292                 compatible = "xlnx,zynqmp-nvmem-fw";
 293                 #address-cells = <1>;
 294                 #size-cells = <1>;
 295
 296                 soc_revision: soc_revision@0 {
 297                         reg = <0x0 0x4>;
 298                 };
 299         };
 300
 301         pcap: pcap {
 302                 compatible = "xlnx,zynqmp-pcap-fpga";
 303         };
 304
 305         amba_apu: amba_apu@0 {
 306                 compatible = "simple-bus";
 307                 #address-cells = <2>;
 308                 #size-cells = <1>;
 309                 ranges = <0 0 0 0 0xffffffff>;
 310
 311                 gic: interrupt-controller@f9010000 {
 312                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
 313                         #interrupt-cells = <3>;
 314                         reg = <0x0 0xf9010000 0x10000>,
 315                               <0x0 0xf9020000 0x20000>,
 316                               <0x0 0xf9040000 0x20000>,
 317                               <0x0 0xf9060000 0x20000>;
 318                         interrupt-controller;
 319                         interrupt-parent = <&gic>;
 320                         interrupts = <1 9 0xf04>;
 321                 };
 322         };
 323
 324         amba: amba {
 325                 compatible = "simple-bus";
 326                 u-boot,dm-pre-reloc;
 327                 #address-cells = <2>;
 328                 #size-cells = <2>;
 329                 ranges;
 330
 331                 can0: can@ff060000 {
 332                         compatible = "xlnx,zynq-can-1.0";
 333                         status = "disabled";
 334                         clock-names = "can_clk", "pclk";
 335                         reg = <0x0 0xff060000 0x0 0x1000>;
 336                         interrupts = <0 23 4>;
 337                         interrupt-parent = <&gic>;
 338                         tx-fifo-depth = <0x40>;
 339                         rx-fifo-depth = <0x40>;
 340                         power-domains = <&pd_can0>;
 341                 };
 342
 343                 can1: can@ff070000 {
 344                         compatible = "xlnx,zynq-can-1.0";
 345                         status = "disabled";
 346                         clock-names = "can_clk", "pclk";
 347                         reg = <0x0 0xff070000 0x0 0x1000>;
 348                         interrupts = <0 24 4>;
 349                         interrupt-parent = <&gic>;
 350                         tx-fifo-depth = <0x40>;
 351                         rx-fifo-depth = <0x40>;
 352                         power-domains = <&pd_can1>;
 353                 };
 354
 355                 cci: cci@fd6e0000 {
 356                         compatible = "arm,cci-400";
 357                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 358                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 359                         #address-cells = <1>;
 360                         #size-cells = <1>;
 361
 362                         pmu@9000 {
 363                                 compatible = "arm,cci-400-pmu,r1";
 364                                 reg = <0x9000 0x5000>;
 365                                 interrupt-parent = <&gic>;
 366                                 interrupts = <0 123 4>,
 367                                              <0 123 4>,
 368                                              <0 123 4>,
 369                                              <0 123 4>,
 370                                              <0 123 4>;
 371                         };
 372                 };
 373
 374                 /* GDMA */
 375                 fpd_dma_chan1: dma@fd500000 {
 376                         status = "disabled";
 377                         compatible = "xlnx,zynqmp-dma-1.0";
 378                         reg = <0x0 0xfd500000 0x0 0x1000>;
 379                         interrupt-parent = <&gic>;
 380                         interrupts = <0 124 4>;
 381                         clock-names = "clk_main", "clk_apb";
 382                         xlnx,bus-width = <128>;
 383                         #stream-id-cells = <1>;
 384                         iommus = <&smmu 0x14e8>;
 385                         power-domains = <&pd_gdma>;
 386                 };
 387
 388                 fpd_dma_chan2: dma@fd510000 {
 389                         status = "disabled";
 390                         compatible = "xlnx,zynqmp-dma-1.0";
 391                         reg = <0x0 0xfd510000 0x0 0x1000>;
 392                         interrupt-parent = <&gic>;
 393                         interrupts = <0 125 4>;
 394                         clock-names = "clk_main", "clk_apb";
 395                         xlnx,bus-width = <128>;
 396                         #stream-id-cells = <1>;
 397                         iommus = <&smmu 0x14e9>;
 398                         power-domains = <&pd_gdma>;
 399                 };
 400
 401                 fpd_dma_chan3: dma@fd520000 {
 402                         status = "disabled";
 403                         compatible = "xlnx,zynqmp-dma-1.0";
 404                         reg = <0x0 0xfd520000 0x0 0x1000>;
 405                         interrupt-parent = <&gic>;
 406                         interrupts = <0 126 4>;
 407                         clock-names = "clk_main", "clk_apb";
 408                         xlnx,bus-width = <128>;
 409                         #stream-id-cells = <1>;
 410                         iommus = <&smmu 0x14ea>;
 411                         power-domains = <&pd_gdma>;
 412                 };
 413
 414                 fpd_dma_chan4: dma@fd530000 {
 415                         status = "disabled";
 416                         compatible = "xlnx,zynqmp-dma-1.0";
 417                         reg = <0x0 0xfd530000 0x0 0x1000>;
 418                         interrupt-parent = <&gic>;
 419                         interrupts = <0 127 4>;
 420                         clock-names = "clk_main", "clk_apb";
 421                         xlnx,bus-width = <128>;
 422                         #stream-id-cells = <1>;
 423                         iommus = <&smmu 0x14eb>;
 424                         power-domains = <&pd_gdma>;
 425                 };
 426
 427                 fpd_dma_chan5: dma@fd540000 {
 428                         status = "disabled";
 429                         compatible = "xlnx,zynqmp-dma-1.0";
 430                         reg = <0x0 0xfd540000 0x0 0x1000>;
 431                         interrupt-parent = <&gic>;
 432                         interrupts = <0 128 4>;
 433                         clock-names = "clk_main", "clk_apb";
 434                         xlnx,bus-width = <128>;
 435                         #stream-id-cells = <1>;
 436                         iommus = <&smmu 0x14ec>;
 437                         power-domains = <&pd_gdma>;
 438                 };
 439
 440                 fpd_dma_chan6: dma@fd550000 {
 441                         status = "disabled";
 442                         compatible = "xlnx,zynqmp-dma-1.0";
 443                         reg = <0x0 0xfd550000 0x0 0x1000>;
 444                         interrupt-parent = <&gic>;
 445                         interrupts = <0 129 4>;
 446                         clock-names = "clk_main", "clk_apb";
 447                         xlnx,bus-width = <128>;
 448                         #stream-id-cells = <1>;
 449                         iommus = <&smmu 0x14ed>;
 450                         power-domains = <&pd_gdma>;
 451                 };
 452
 453                 fpd_dma_chan7: dma@fd560000 {
 454                         status = "disabled";
 455                         compatible = "xlnx,zynqmp-dma-1.0";
 456                         reg = <0x0 0xfd560000 0x0 0x1000>;
 457                         interrupt-parent = <&gic>;
 458                         interrupts = <0 130 4>;
 459                         clock-names = "clk_main", "clk_apb";
 460                         xlnx,bus-width = <128>;
 461                         #stream-id-cells = <1>;
 462                         iommus = <&smmu 0x14ee>;
 463                         power-domains = <&pd_gdma>;
 464                 };
 465
 466                 fpd_dma_chan8: dma@fd570000 {
 467                         status = "disabled";
 468                         compatible = "xlnx,zynqmp-dma-1.0";
 469                         reg = <0x0 0xfd570000 0x0 0x1000>;
 470                         interrupt-parent = <&gic>;
 471                         interrupts = <0 131 4>;
 472                         clock-names = "clk_main", "clk_apb";
 473                         xlnx,bus-width = <128>;
 474                         #stream-id-cells = <1>;
 475                         iommus = <&smmu 0x14ef>;
 476                         power-domains = <&pd_gdma>;
 477                 };
 478
 479                 gpu: gpu@fd4b0000 {
 480                         status = "disabled";
 481                         compatible = "arm,mali-400", "arm,mali-utgard";
 482                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 483                         interrupt-parent = <&gic>;
 484                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 485                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 486                         clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 487                         power-domains = <&pd_gpu>;
 488                 };
 489
 490                 /* LPDDMA default allows only secured access. inorder to enable
 491                  * These dma channels, Users should ensure that these dma
 492                  * Channels are allowed for non secure access.
 493                  */
 494                 lpd_dma_chan1: dma@ffa80000 {
 495                         status = "disabled";
 496                         compatible = "xlnx,zynqmp-dma-1.0";
 497                         clock-names = "clk_main", "clk_apb";
 498                         reg = <0x0 0xffa80000 0x0 0x1000>;
 499                         interrupt-parent = <&gic>;
 500                         interrupts = <0 77 4>;
 501                         xlnx,bus-width = <64>;
 502                         #stream-id-cells = <1>;
 503                         iommus = <&smmu 0x868>;
 504                         power-domains = <&pd_adma>;
 505                 };
 506
 507                 lpd_dma_chan2: dma@ffa90000 {
 508                         status = "disabled";
 509                         compatible = "xlnx,zynqmp-dma-1.0";
 510                         clock-names = "clk_main", "clk_apb";
 511                         reg = <0x0 0xffa90000 0x0 0x1000>;
 512                         interrupt-parent = <&gic>;
 513                         interrupts = <0 78 4>;
 514                         xlnx,bus-width = <64>;
 515                         #stream-id-cells = <1>;
 516                         iommus = <&smmu 0x869>;
 517                         power-domains = <&pd_adma>;
 518                 };
 519
 520                 lpd_dma_chan3: dma@ffaa0000 {
 521                         status = "disabled";
 522                         compatible = "xlnx,zynqmp-dma-1.0";
 523                         clock-names = "clk_main", "clk_apb";
 524                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 525                         interrupt-parent = <&gic>;
 526                         interrupts = <0 79 4>;
 527                         xlnx,bus-width = <64>;
 528                         #stream-id-cells = <1>;
 529                         iommus = <&smmu 0x86a>;
 530                         power-domains = <&pd_adma>;
 531                 };
 532
 533                 lpd_dma_chan4: dma@ffab0000 {
 534                         status = "disabled";
 535                         compatible = "xlnx,zynqmp-dma-1.0";
 536                         clock-names = "clk_main", "clk_apb";
 537                         reg = <0x0 0xffab0000 0x0 0x1000>;
 538                         interrupt-parent = <&gic>;
 539                         interrupts = <0 80 4>;
 540                         xlnx,bus-width = <64>;
 541                         #stream-id-cells = <1>;
 542                         iommus = <&smmu 0x86b>;
 543                         power-domains = <&pd_adma>;
 544                 };
 545
 546                 lpd_dma_chan5: dma@ffac0000 {
 547                         status = "disabled";
 548                         compatible = "xlnx,zynqmp-dma-1.0";
 549                         clock-names = "clk_main", "clk_apb";
 550                         reg = <0x0 0xffac0000 0x0 0x1000>;
 551                         interrupt-parent = <&gic>;
 552                         interrupts = <0 81 4>;
 553                         xlnx,bus-width = <64>;
 554                         #stream-id-cells = <1>;
 555                         iommus = <&smmu 0x86c>;
 556                         power-domains = <&pd_adma>;
 557                 };
 558
 559                 lpd_dma_chan6: dma@ffad0000 {
 560                         status = "disabled";
 561                         compatible = "xlnx,zynqmp-dma-1.0";
 562                         clock-names = "clk_main", "clk_apb";
 563                         reg = <0x0 0xffad0000 0x0 0x1000>;
 564                         interrupt-parent = <&gic>;
 565                         interrupts = <0 82 4>;
 566                         xlnx,bus-width = <64>;
 567                         #stream-id-cells = <1>;
 568                         iommus = <&smmu 0x86d>;
 569                         power-domains = <&pd_adma>;
 570                 };
 571
 572                 lpd_dma_chan7: dma@ffae0000 {
 573                         status = "disabled";
 574                         compatible = "xlnx,zynqmp-dma-1.0";
 575                         clock-names = "clk_main", "clk_apb";
 576                         reg = <0x0 0xffae0000 0x0 0x1000>;
 577                         interrupt-parent = <&gic>;
 578                         interrupts = <0 83 4>;
 579                         xlnx,bus-width = <64>;
 580                         #stream-id-cells = <1>;
 581                         iommus = <&smmu 0x86e>;
 582                         power-domains = <&pd_adma>;
 583                 };
 584
 585                 lpd_dma_chan8: dma@ffaf0000 {
 586                         status = "disabled";
 587                         compatible = "xlnx,zynqmp-dma-1.0";
 588                         clock-names = "clk_main", "clk_apb";
 589                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 590                         interrupt-parent = <&gic>;
 591                         interrupts = <0 84 4>;
 592                         xlnx,bus-width = <64>;
 593                         #stream-id-cells = <1>;
 594                         iommus = <&smmu 0x86f>;
 595                         power-domains = <&pd_adma>;
 596                 };
 597
 598                 mc: memory-controller@fd070000 {
 599                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 600                         reg = <0x0 0xfd070000 0x0 0x30000>;
 601                         interrupt-parent = <&gic>;
 602                         interrupts = <0 112 4>;
 603                 };
 604
 605                 nand0: nand@ff100000 {
 606                         compatible = "arasan,nfc-v3p10";
 607                         status = "disabled";
 608                         reg = <0x0 0xff100000 0x0 0x1000>;
 609                         clock-names = "clk_sys", "clk_flash";
 610                         interrupt-parent = <&gic>;
 611                         interrupts = <0 14 4>;
 612                         #address-cells = <2>;
 613                         #size-cells = <1>;
 614                         #stream-id-cells = <1>;
 615                         iommus = <&smmu 0x872>;
 616                         power-domains = <&pd_nand>;
 617                 };
 618
 619                 gem0: ethernet@ff0b0000 {
 620                         compatible = "cdns,zynqmp-gem";
 621                         status = "disabled";
 622                         interrupt-parent = <&gic>;
 623                         interrupts = <0 57 4>, <0 57 4>;
 624                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 625                         clock-names = "pclk", "hclk", "tx_clk";
 626                         #address-cells = <1>;
 627                         #size-cells = <0>;
 628                         #stream-id-cells = <1>;
 629                         iommus = <&smmu 0x874>;
 630                         power-domains = <&pd_eth0>;
 631                 };
 632
 633                 gem1: ethernet@ff0c0000 {
 634                         compatible = "cdns,zynqmp-gem";
 635                         status = "disabled";
 636                         interrupt-parent = <&gic>;
 637                         interrupts = <0 59 4>, <0 59 4>;
 638                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 639                         clock-names = "pclk", "hclk", "tx_clk";
 640                         #address-cells = <1>;
 641                         #size-cells = <0>;
 642                         #stream-id-cells = <1>;
 643                         iommus = <&smmu 0x875>;
 644                         power-domains = <&pd_eth1>;
 645                 };
 646
 647                 gem2: ethernet@ff0d0000 {
 648                         compatible = "cdns,zynqmp-gem";
 649                         status = "disabled";
 650                         interrupt-parent = <&gic>;
 651                         interrupts = <0 61 4>, <0 61 4>;
 652                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 653                         clock-names = "pclk", "hclk", "tx_clk";
 654                         #address-cells = <1>;
 655                         #size-cells = <0>;
 656                         #stream-id-cells = <1>;
 657                         iommus = <&smmu 0x876>;
 658                         power-domains = <&pd_eth2>;
 659                 };
 660
 661                 gem3: ethernet@ff0e0000 {
 662                         compatible = "cdns,zynqmp-gem";
 663                         status = "disabled";
 664                         interrupt-parent = <&gic>;
 665                         interrupts = <0 63 4>, <0 63 4>;
 666                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 667                         clock-names = "pclk", "hclk", "tx_clk";
 668                         #address-cells = <1>;
 669                         #size-cells = <0>;
 670                         #stream-id-cells = <1>;
 671                         iommus = <&smmu 0x877>;
 672                         power-domains = <&pd_eth3>;
 673                 };
 674
 675                 gpio: gpio@ff0a0000 {
 676                         compatible = "xlnx,zynqmp-gpio-1.0";
 677                         status = "disabled";
 678                         #gpio-cells = <0x2>;
 679                         interrupt-parent = <&gic>;
 680                         interrupts = <0 16 4>;
 681                         interrupt-controller;
 682                         #interrupt-cells = <2>;
 683                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 684                         gpio-controller;
 685                         power-domains = <&pd_gpio>;
 686                 };
 687
 688                 i2c0: i2c@ff020000 {
 689                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 690                         status = "disabled";
 691                         interrupt-parent = <&gic>;
 692                         interrupts = <0 17 4>;
 693                         reg = <0x0 0xff020000 0x0 0x1000>;
 694                         #address-cells = <1>;
 695                         #size-cells = <0>;
 696                         power-domains = <&pd_i2c0>;
 697                 };
 698
 699                 i2c1: i2c@ff030000 {
 700                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 701                         status = "disabled";
 702                         interrupt-parent = <&gic>;
 703                         interrupts = <0 18 4>;
 704                         reg = <0x0 0xff030000 0x0 0x1000>;
 705                         #address-cells = <1>;
 706                         #size-cells = <0>;
 707                         power-domains = <&pd_i2c1>;
 708                 };
 709
 710                 ocm: memory-controller@ff960000 {
 711                         compatible = "xlnx,zynqmp-ocmc-1.0";
 712                         reg = <0x0 0xff960000 0x0 0x1000>;
 713                         interrupt-parent = <&gic>;
 714                         interrupts = <0 10 4>;
 715                 };
 716
 717                 pcie: pcie@fd0e0000 {
 718                         compatible = "xlnx,nwl-pcie-2.11";
 719                         status = "disabled";
 720                         #address-cells = <3>;
 721                         #size-cells = <2>;
 722                         #interrupt-cells = <1>;
 723                         msi-controller;
 724                         device_type = "pci";
 725                         interrupt-parent = <&gic>;
 726                         interrupts = <0 118 4>,
 727                                      <0 117 4>,
 728                                      <0 116 4>,
 729                                      <0 115 4>, /* MSI_1 [63...32] */
 730                                      <0 114 4>; /* MSI_0 [31...0] */
 731                         interrupt-names = "misc","dummy","intx", "msi1", "msi0";
 732                         msi-parent = <&pcie>;
 733                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 734                               <0x0 0xfd480000 0x0 0x1000>,
 735                               <0x80 0x00000000 0x0 0x1000000>;
 736                         reg-names = "breg", "pcireg", "cfg";
 737                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 738                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 739                         bus-range = <0x00 0xff>;
 740                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 741                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 742                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 743                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 744                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 745                         power-domains = <&pd_pcie>;
 746                         pcie_intc: legacy-interrupt-controller {
 747                                 interrupt-controller;
 748                                 #address-cells = <0>;
 749                                 #interrupt-cells = <1>;
 750                         };
 751                 };
 752
 753                 qspi: spi@ff0f0000 {
 754                         compatible = "xlnx,zynqmp-qspi-1.0";
 755                         status = "disabled";
 756                         clock-names = "ref_clk", "pclk";
 757                         interrupts = <0 15 4>;
 758                         interrupt-parent = <&gic>;
 759                         num-cs = <1>;
 760                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 761                               <0x0 0xc0000000 0x0 0x8000000>;
 762                         #address-cells = <1>;
 763                         #size-cells = <0>;
 764                         #stream-id-cells = <1>;
 765                         iommus = <&smmu 0x873>;
 766                         power-domains = <&pd_qspi>;
 767                 };
 768
 769                 rtc: rtc@ffa60000 {
 770                         compatible = "xlnx,zynqmp-rtc";
 771                         status = "disabled";
 772                         reg = <0x0 0xffa60000 0x0 0x100>;
 773                         interrupt-parent = <&gic>;
 774                         interrupts = <0 26 4>, <0 27 4>;
 775                         interrupt-names = "alarm", "sec";
 776                         calibration = <0x8000>;
 777                 };
 778
 779                 serdes: zynqmp_phy@fd400000 {
 780                         compatible = "xlnx,zynqmp-psgtr";
 781                         status = "disabled";
 782                         reg = <0x0 0xfd400000 0x0 0x40000>,
 783                               <0x0 0xfd3d0000 0x0 0x1000>,
 784                               <0x0 0xfd1a0000 0x0 0x1000>,
 785                               <0x0 0xff5e0000 0x0 0x1000>;
 786                         reg-names = "serdes", "siou", "fpd", "lpd";
 787                         nvmem-cells = <&soc_revision>;
 788                         nvmem-cell-names = "soc_revision";
 789                         lane0: lane0 {
 790                                 #phy-cells = <4>;
 791                         };
 792                         lane1: lane1 {
 793                                 #phy-cells = <4>;
 794                         };
 795                         lane2: lane2 {
 796                                 #phy-cells = <4>;
 797                         };
 798                         lane3: lane3 {
 799                                 #phy-cells = <4>;
 800                         };
 801                 };
 802
 803                 sata: ahci@fd0c0000 {
 804                         compatible = "ceva,ahci-1v84";
 805                         status = "disabled";
 806                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 807                         interrupt-parent = <&gic>;
 808                         interrupts = <0 133 4>;
 809                         power-domains = <&pd_sata>;
 810                         #stream-id-cells = <4>;
 811                         iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 812                                  <&smmu 0x4c2>, <&smmu 0x4c3>;
 813                         /* dma-coherent; */
 814                 };
 815
 816                 sdhci0: sdhci@ff160000 {
 817                         u-boot,dm-pre-reloc;
 818                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 819                         status = "disabled";
 820                         interrupt-parent = <&gic>;
 821                         interrupts = <0 48 4>;
 822                         reg = <0x0 0xff160000 0x0 0x1000>;
 823                         clock-names = "clk_xin", "clk_ahb";
 824                         xlnx,device_id = <0>;
 825                         #stream-id-cells = <1>;
 826                         iommus = <&smmu 0x870>;
 827                         power-domains = <&pd_sd0>;
 828                 };
 829
 830                 sdhci1: sdhci@ff170000 {
 831                         u-boot,dm-pre-reloc;
 832                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 833                         status = "disabled";
 834                         interrupt-parent = <&gic>;
 835                         interrupts = <0 49 4>;
 836                         reg = <0x0 0xff170000 0x0 0x1000>;
 837                         clock-names = "clk_xin", "clk_ahb";
 838                         xlnx,device_id = <1>;
 839                         #stream-id-cells = <1>;
 840                         iommus = <&smmu 0x871>;
 841                         power-domains = <&pd_sd1>;
 842                 };
 843
 844                 pinctrl0: pinctrl@ff180000 {
 845                         compatible = "xlnx,pinctrl-zynqmp";
 846                         status = "disabled";
 847                         reg = <0x0 0xff180000 0x0 0x1000>;
 848                 };
 849
 850                 smmu: smmu@fd800000 {
 851                         compatible = "arm,mmu-500";
 852                         reg = <0x0 0xfd800000 0x0 0x20000>;
 853                         #iommu-cells = <1>;
 854                         status = "disabled";
 855                         #global-interrupts = <1>;
 856                         interrupt-parent = <&gic>;
 857                         interrupts = <0 155 4>,
 858                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 859                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 860                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 861                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 862                 };
 863
 864                 spi0: spi@ff040000 {
 865                         compatible = "cdns,spi-r1p6";
 866                         status = "disabled";
 867                         interrupt-parent = <&gic>;
 868                         interrupts = <0 19 4>;
 869                         reg = <0x0 0xff040000 0x0 0x1000>;
 870                         clock-names = "ref_clk", "pclk";
 871                         #address-cells = <1>;
 872                         #size-cells = <0>;
 873                         power-domains = <&pd_spi0>;
 874                 };
 875
 876                 spi1: spi@ff050000 {
 877                         compatible = "cdns,spi-r1p6";
 878                         status = "disabled";
 879                         interrupt-parent = <&gic>;
 880                         interrupts = <0 20 4>;
 881                         reg = <0x0 0xff050000 0x0 0x1000>;
 882                         clock-names = "ref_clk", "pclk";
 883                         #address-cells = <1>;
 884                         #size-cells = <0>;
 885                         power-domains = <&pd_spi1>;
 886                 };
 887
 888                 ttc0: timer@ff110000 {
 889                         compatible = "cdns,ttc";
 890                         status = "disabled";
 891                         interrupt-parent = <&gic>;
 892                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 893                         reg = <0x0 0xff110000 0x0 0x1000>;
 894                         timer-width = <32>;
 895                         power-domains = <&pd_ttc0>;
 896                 };
 897
 898                 ttc1: timer@ff120000 {
 899                         compatible = "cdns,ttc";
 900                         status = "disabled";
 901                         interrupt-parent = <&gic>;
 902                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 903                         reg = <0x0 0xff120000 0x0 0x1000>;
 904                         timer-width = <32>;
 905                         power-domains = <&pd_ttc1>;
 906                 };
 907
 908                 ttc2: timer@ff130000 {
 909                         compatible = "cdns,ttc";
 910                         status = "disabled";
 911                         interrupt-parent = <&gic>;
 912                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 913                         reg = <0x0 0xff130000 0x0 0x1000>;
 914                         timer-width = <32>;
 915                         power-domains = <&pd_ttc2>;
 916                 };
 917
 918                 ttc3: timer@ff140000 {
 919                         compatible = "cdns,ttc";
 920                         status = "disabled";
 921                         interrupt-parent = <&gic>;
 922                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 923                         reg = <0x0 0xff140000 0x0 0x1000>;
 924                         timer-width = <32>;
 925                         power-domains = <&pd_ttc3>;
 926                 };
 927
 928                 uart0: serial@ff000000 {
 929                         u-boot,dm-pre-reloc;
 930                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 931                         status = "disabled";
 932                         interrupt-parent = <&gic>;
 933                         interrupts = <0 21 4>;
 934                         reg = <0x0 0xff000000 0x0 0x1000>;
 935                         clock-names = "uart_clk", "pclk";
 936                         power-domains = <&pd_uart0>;
 937                 };
 938
 939                 uart1: serial@ff010000 {
 940                         u-boot,dm-pre-reloc;
 941                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 942                         status = "disabled";
 943                         interrupt-parent = <&gic>;
 944                         interrupts = <0 22 4>;
 945                         reg = <0x0 0xff010000 0x0 0x1000>;
 946                         clock-names = "uart_clk", "pclk";
 947                         power-domains = <&pd_uart1>;
 948                 };
 949
 950                 usb0: usb0 {
 951                         #address-cells = <2>;
 952                         #size-cells = <2>;
 953                         status = "disabled";
 954                         compatible = "xlnx,zynqmp-dwc3";
 955                         clock-names = "bus_clk", "ref_clk";
 956                         clocks = <&clk125>, <&clk125>;
 957                         #stream-id-cells = <1>;
 958                         iommus = <&smmu 0x860>;
 959                         power-domains = <&pd_usb0>;
 960                         ranges;
 961
 962                         dwc3_0: dwc3@fe200000 {
 963                                 compatible = "snps,dwc3";
 964                                 status = "disabled";
 965                                 reg = <0x0 0xfe200000 0x0 0x40000>;
 966                                 interrupt-parent = <&gic>;
 967                                 interrupts = <0 65 4>;
 968                                 /* snps,quirk-frame-length-adjustment = <0x20>; */
 969                                 snps,refclk_fladj;
 970                         };
 971                 };
 972
 973                 usb1: usb1 {
 974                         #address-cells = <2>;
 975                         #size-cells = <2>;
 976                         status = "disabled";
 977                         compatible = "xlnx,zynqmp-dwc3";
 978                         clock-names = "bus_clk", "ref_clk";
 979                         clocks = <&clk125>, <&clk125>;
 980                         #stream-id-cells = <1>;
 981                         iommus = <&smmu 0x861>;
 982                         power-domains = <&pd_usb1>;
 983                         ranges;
 984
 985                         dwc3_1: dwc3@fe300000 {
 986                                 compatible = "snps,dwc3";
 987                                 status = "disabled";
 988                                 reg = <0x0 0xfe300000 0x0 0x40000>;
 989                                 interrupt-parent = <&gic>;
 990                                 interrupts = <0 70 4>;
 991                                 /* snps,quirk-frame-length-adjustment = <0x20>; */
 992                                 snps,refclk_fladj;
 993                         };
 994                 };
 995
 996                 watchdog0: watchdog@fd4d0000 {
 997                         compatible = "cdns,wdt-r1p2";
 998                         status = "disabled";
 999                         interrupt-parent = <&gic>;
1000                         interrupts = <0 113 1>;
1001                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
1002                         timeout-sec = <10>;
1003                 };
1004
1005                 xilinx_drm: xilinx_drm {
1006                         compatible = "xlnx,drm";
1007                         status = "disabled";
1008                         xlnx,encoder-slave = <&xlnx_dp>;
1009                         xlnx,connector-type = "DisplayPort";
1010                         xlnx,dp-sub = <&xlnx_dp_sub>;
1011                         planes {
1012                                 xlnx,pixel-format = "rgb565";
1013                                 plane0 {
1014                                         dmas = <&xlnx_dpdma 3>;
1015                                         dma-names = "dma0";
1016                                 };
1017                                 plane1 {
1018                                         dmas = <&xlnx_dpdma 0>,
1019                                                <&xlnx_dpdma 1>,
1020                                                <&xlnx_dpdma 2>;
1021                                         dma-names = "dma0", "dma1", "dma2";
1022                                 };
1023                         };
1024                 };
1025
1026                 xlnx_dp: dp@fd4a0000 {
1027                         compatible = "xlnx,v-dp";
1028                         status = "disabled";
1029                         reg = <0x0 0xfd4a0000 0x0 0x1000>;
1030                         interrupts = <0 119 4>;
1031                         interrupt-parent = <&gic>;
1032                         clock-names = "aclk", "aud_clk";
1033                         power-domains = <&pd_dp>;
1034                         xlnx,dp-version = "v1.2";
1035                         xlnx,max-lanes = <2>;
1036                         xlnx,max-link-rate = <540000>;
1037                         xlnx,max-bpc = <16>;
1038                         xlnx,enable-ycrcb;
1039                         xlnx,colormetry = "rgb";
1040                         xlnx,bpc = <8>;
1041                         xlnx,audio-chan = <2>;
1042                         xlnx,dp-sub = <&xlnx_dp_sub>;
1043                         xlnx,max-pclock-frequency = <300000>;
1044                 };
1045
1046                 xlnx_dp_snd_card: dp_snd_card {
1047                         compatible = "xlnx,dp-snd-card";
1048                         status = "disabled";
1049                         xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
1050                         xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
1051                 };
1052
1053                 xlnx_dp_snd_codec0: dp_snd_codec0 {
1054                         compatible = "xlnx,dp-snd-codec";
1055                         status = "disabled";
1056                         clock-names = "aud_clk";
1057                 };
1058
1059                 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
1060                         compatible = "xlnx,dp-snd-pcm";
1061                         status = "disabled";
1062                         dmas = <&xlnx_dpdma 4>;
1063                         dma-names = "tx";
1064                 };
1065
1066                 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1067                         compatible = "xlnx,dp-snd-pcm";
1068                         status = "disabled";
1069                         dmas = <&xlnx_dpdma 5>;
1070                         dma-names = "tx";
1071                 };
1072
1073                 xlnx_dp_sub: dp_sub@fd4aa000 {
1074                         compatible = "xlnx,dp-sub";
1075                         status = "disabled";
1076                         reg = <0x0 0xfd4aa000 0x0 0x1000>,
1077                               <0x0 0xfd4ab000 0x0 0x1000>,
1078                               <0x0 0xfd4ac000 0x0 0x1000>;
1079                         reg-names = "blend", "av_buf", "aud";
1080                         xlnx,output-fmt = "rgb";
1081                         xlnx,vid-fmt = "yuyv";
1082                         xlnx,gfx-fmt = "rgb565";
1083                         power-domains = <&pd_dp>;
1084                 };
1085
1086                 xlnx_dpdma: dma@fd4c0000 {
1087                         compatible = "xlnx,dpdma";
1088                         status = "disabled";
1089                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
1090                         interrupts = <0 122 4>;
1091                         interrupt-parent = <&gic>;
1092                         clock-names = "axi_clk";
1093                         power-domains = <&pd_dp>;
1094                         dma-channels = <6>;
1095                         #dma-cells = <1>;
1096                         dma-video0channel {
1097                                 compatible = "xlnx,video0";
1098                         };
1099                         dma-video1channel {
1100                                 compatible = "xlnx,video1";
1101                         };
1102                         dma-video2channel {
1103                                 compatible = "xlnx,video2";
1104                         };
1105                         dma-graphicschannel {
1106                                 compatible = "xlnx,graphics";
1107                         };
1108                         dma-audio0channel {
1109                                 compatible = "xlnx,audio0";
1110                         };
1111                         dma-audio1channel {
1112                                 compatible = "xlnx,audio1";
1113                         };
1114                 };
1115         };
1116 };