2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 compatible = "xlnx,zynqmp";
21 compatible = "arm,cortex-a53", "arm,armv8";
23 enable-method = "psci";
24 operating-points-v2 = <&cpu_opp_table>;
26 cpu-idle-states = <&CPU_SLEEP_0>;
30 compatible = "arm,cortex-a53", "arm,armv8";
32 enable-method = "psci";
34 operating-points-v2 = <&cpu_opp_table>;
35 cpu-idle-states = <&CPU_SLEEP_0>;
39 compatible = "arm,cortex-a53", "arm,armv8";
41 enable-method = "psci";
43 operating-points-v2 = <&cpu_opp_table>;
44 cpu-idle-states = <&CPU_SLEEP_0>;
48 compatible = "arm,cortex-a53", "arm,armv8";
50 enable-method = "psci";
52 operating-points-v2 = <&cpu_opp_table>;
53 cpu-idle-states = <&CPU_SLEEP_0>;
57 entry-method = "arm,psci";
59 CPU_SLEEP_0: cpu-sleep-0 {
60 compatible = "arm,idle-state";
61 arm,psci-suspend-param = <0x40000000>;
63 entry-latency-us = <300>;
64 exit-latency-us = <600>;
65 min-residency-us = <10000>;
70 cpu_opp_table: cpu_opp_table {
71 compatible = "operating-points-v2";
74 opp-hz = /bits/ 64 <1199999988>;
75 opp-microvolt = <1000000>;
76 clock-latency-ns = <500000>;
79 opp-hz = /bits/ 64 <599999994>;
80 opp-microvolt = <1000000>;
81 clock-latency-ns = <500000>;
84 opp-hz = /bits/ 64 <399999996>;
85 opp-microvolt = <1000000>;
86 clock-latency-ns = <500000>;
89 opp-hz = /bits/ 64 <299999997>;
90 opp-microvolt = <1000000>;
91 clock-latency-ns = <500000>;
96 compatible = "arm,dcc";
102 compatible = "xlnx,zynqmp-genpd";
105 #power-domain-cells = <0x0>;
110 #power-domain-cells = <0x0>;
115 #power-domain-cells = <0x0>;
120 #power-domain-cells = <0x0>;
125 #power-domain-cells = <0x0>;
130 #power-domain-cells = <0x0>;
135 #power-domain-cells = <0x0>;
140 #power-domain-cells = <0x0>;
145 #power-domain-cells = <0x0>;
150 #power-domain-cells = <0x0>;
155 #power-domain-cells = <0x0>;
160 #power-domain-cells = <0x0>;
165 #power-domain-cells = <0x0>;
170 #power-domain-cells = <0x0>;
175 #power-domain-cells = <0x0>;
180 #power-domain-cells = <0x0>;
185 #power-domain-cells = <0x0>;
190 #power-domain-cells = <0x0>;
195 #power-domain-cells = <0x0>;
200 #power-domain-cells = <0x0>;
205 #power-domain-cells = <0x0>;
210 #power-domain-cells = <0x0>;
215 #power-domain-cells = <0x0>;
220 #power-domain-cells = <0x0>;
225 #power-domain-cells = <0x0>;
230 #power-domain-cells = <0x0>;
235 #power-domain-cells = <0x0>;
240 #power-domain-cells = <0x0>;
245 #power-domain-cells = <0x0>;
246 pd-id = <0x3a 0x14 0x15>;
251 compatible = "arm,armv8-pmuv3";
252 interrupt-parent = <&gic>;
253 interrupts = <0 143 4>,
260 compatible = "arm,psci-0.2";
265 compatible = "xlnx,zynqmp-pm";
267 interrupt-parent = <&gic>;
268 interrupts = <0 35 4>;
272 compatible = "arm,armv8-timer";
273 interrupt-parent = <&gic>;
274 interrupts = <1 13 0xf08>,
281 compatible = "arm,cortex-a53-edac";
284 fpga_full: fpga-full {
285 compatible = "fpga-region";
287 #address-cells = <2>;
292 compatible = "xlnx,zynqmp-nvmem-fw";
293 #address-cells = <1>;
296 soc_revision: soc_revision@0 {
302 compatible = "xlnx,zynqmp-pcap-fpga";
305 amba_apu: amba_apu@0 {
306 compatible = "simple-bus";
307 #address-cells = <2>;
309 ranges = <0 0 0 0 0xffffffff>;
311 gic: interrupt-controller@f9010000 {
312 compatible = "arm,gic-400", "arm,cortex-a15-gic";
313 #interrupt-cells = <3>;
314 reg = <0x0 0xf9010000 0x10000>,
315 <0x0 0xf9020000 0x20000>,
316 <0x0 0xf9040000 0x20000>,
317 <0x0 0xf9060000 0x20000>;
318 interrupt-controller;
319 interrupt-parent = <&gic>;
320 interrupts = <1 9 0xf04>;
325 compatible = "simple-bus";
327 #address-cells = <2>;
332 compatible = "xlnx,zynq-can-1.0";
334 clock-names = "can_clk", "pclk";
335 reg = <0x0 0xff060000 0x0 0x1000>;
336 interrupts = <0 23 4>;
337 interrupt-parent = <&gic>;
338 tx-fifo-depth = <0x40>;
339 rx-fifo-depth = <0x40>;
340 power-domains = <&pd_can0>;
344 compatible = "xlnx,zynq-can-1.0";
346 clock-names = "can_clk", "pclk";
347 reg = <0x0 0xff070000 0x0 0x1000>;
348 interrupts = <0 24 4>;
349 interrupt-parent = <&gic>;
350 tx-fifo-depth = <0x40>;
351 rx-fifo-depth = <0x40>;
352 power-domains = <&pd_can1>;
356 compatible = "arm,cci-400";
357 reg = <0x0 0xfd6e0000 0x0 0x9000>;
358 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
359 #address-cells = <1>;
363 compatible = "arm,cci-400-pmu,r1";
364 reg = <0x9000 0x5000>;
365 interrupt-parent = <&gic>;
366 interrupts = <0 123 4>,
375 fpd_dma_chan1: dma@fd500000 {
377 compatible = "xlnx,zynqmp-dma-1.0";
378 reg = <0x0 0xfd500000 0x0 0x1000>;
379 interrupt-parent = <&gic>;
380 interrupts = <0 124 4>;
381 clock-names = "clk_main", "clk_apb";
382 xlnx,bus-width = <128>;
383 #stream-id-cells = <1>;
384 iommus = <&smmu 0x14e8>;
385 power-domains = <&pd_gdma>;
388 fpd_dma_chan2: dma@fd510000 {
390 compatible = "xlnx,zynqmp-dma-1.0";
391 reg = <0x0 0xfd510000 0x0 0x1000>;
392 interrupt-parent = <&gic>;
393 interrupts = <0 125 4>;
394 clock-names = "clk_main", "clk_apb";
395 xlnx,bus-width = <128>;
396 #stream-id-cells = <1>;
397 iommus = <&smmu 0x14e9>;
398 power-domains = <&pd_gdma>;
401 fpd_dma_chan3: dma@fd520000 {
403 compatible = "xlnx,zynqmp-dma-1.0";
404 reg = <0x0 0xfd520000 0x0 0x1000>;
405 interrupt-parent = <&gic>;
406 interrupts = <0 126 4>;
407 clock-names = "clk_main", "clk_apb";
408 xlnx,bus-width = <128>;
409 #stream-id-cells = <1>;
410 iommus = <&smmu 0x14ea>;
411 power-domains = <&pd_gdma>;
414 fpd_dma_chan4: dma@fd530000 {
416 compatible = "xlnx,zynqmp-dma-1.0";
417 reg = <0x0 0xfd530000 0x0 0x1000>;
418 interrupt-parent = <&gic>;
419 interrupts = <0 127 4>;
420 clock-names = "clk_main", "clk_apb";
421 xlnx,bus-width = <128>;
422 #stream-id-cells = <1>;
423 iommus = <&smmu 0x14eb>;
424 power-domains = <&pd_gdma>;
427 fpd_dma_chan5: dma@fd540000 {
429 compatible = "xlnx,zynqmp-dma-1.0";
430 reg = <0x0 0xfd540000 0x0 0x1000>;
431 interrupt-parent = <&gic>;
432 interrupts = <0 128 4>;
433 clock-names = "clk_main", "clk_apb";
434 xlnx,bus-width = <128>;
435 #stream-id-cells = <1>;
436 iommus = <&smmu 0x14ec>;
437 power-domains = <&pd_gdma>;
440 fpd_dma_chan6: dma@fd550000 {
442 compatible = "xlnx,zynqmp-dma-1.0";
443 reg = <0x0 0xfd550000 0x0 0x1000>;
444 interrupt-parent = <&gic>;
445 interrupts = <0 129 4>;
446 clock-names = "clk_main", "clk_apb";
447 xlnx,bus-width = <128>;
448 #stream-id-cells = <1>;
449 iommus = <&smmu 0x14ed>;
450 power-domains = <&pd_gdma>;
453 fpd_dma_chan7: dma@fd560000 {
455 compatible = "xlnx,zynqmp-dma-1.0";
456 reg = <0x0 0xfd560000 0x0 0x1000>;
457 interrupt-parent = <&gic>;
458 interrupts = <0 130 4>;
459 clock-names = "clk_main", "clk_apb";
460 xlnx,bus-width = <128>;
461 #stream-id-cells = <1>;
462 iommus = <&smmu 0x14ee>;
463 power-domains = <&pd_gdma>;
466 fpd_dma_chan8: dma@fd570000 {
468 compatible = "xlnx,zynqmp-dma-1.0";
469 reg = <0x0 0xfd570000 0x0 0x1000>;
470 interrupt-parent = <&gic>;
471 interrupts = <0 131 4>;
472 clock-names = "clk_main", "clk_apb";
473 xlnx,bus-width = <128>;
474 #stream-id-cells = <1>;
475 iommus = <&smmu 0x14ef>;
476 power-domains = <&pd_gdma>;
481 compatible = "arm,mali-400", "arm,mali-utgard";
482 reg = <0x0 0xfd4b0000 0x0 0x10000>;
483 interrupt-parent = <&gic>;
484 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
485 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
486 clock-names = "gpu", "gpu_pp0", "gpu_pp1";
487 power-domains = <&pd_gpu>;
490 /* LPDDMA default allows only secured access. inorder to enable
491 * These dma channels, Users should ensure that these dma
492 * Channels are allowed for non secure access.
494 lpd_dma_chan1: dma@ffa80000 {
496 compatible = "xlnx,zynqmp-dma-1.0";
497 clock-names = "clk_main", "clk_apb";
498 reg = <0x0 0xffa80000 0x0 0x1000>;
499 interrupt-parent = <&gic>;
500 interrupts = <0 77 4>;
501 xlnx,bus-width = <64>;
502 #stream-id-cells = <1>;
503 iommus = <&smmu 0x868>;
504 power-domains = <&pd_adma>;
507 lpd_dma_chan2: dma@ffa90000 {
509 compatible = "xlnx,zynqmp-dma-1.0";
510 clock-names = "clk_main", "clk_apb";
511 reg = <0x0 0xffa90000 0x0 0x1000>;
512 interrupt-parent = <&gic>;
513 interrupts = <0 78 4>;
514 xlnx,bus-width = <64>;
515 #stream-id-cells = <1>;
516 iommus = <&smmu 0x869>;
517 power-domains = <&pd_adma>;
520 lpd_dma_chan3: dma@ffaa0000 {
522 compatible = "xlnx,zynqmp-dma-1.0";
523 clock-names = "clk_main", "clk_apb";
524 reg = <0x0 0xffaa0000 0x0 0x1000>;
525 interrupt-parent = <&gic>;
526 interrupts = <0 79 4>;
527 xlnx,bus-width = <64>;
528 #stream-id-cells = <1>;
529 iommus = <&smmu 0x86a>;
530 power-domains = <&pd_adma>;
533 lpd_dma_chan4: dma@ffab0000 {
535 compatible = "xlnx,zynqmp-dma-1.0";
536 clock-names = "clk_main", "clk_apb";
537 reg = <0x0 0xffab0000 0x0 0x1000>;
538 interrupt-parent = <&gic>;
539 interrupts = <0 80 4>;
540 xlnx,bus-width = <64>;
541 #stream-id-cells = <1>;
542 iommus = <&smmu 0x86b>;
543 power-domains = <&pd_adma>;
546 lpd_dma_chan5: dma@ffac0000 {
548 compatible = "xlnx,zynqmp-dma-1.0";
549 clock-names = "clk_main", "clk_apb";
550 reg = <0x0 0xffac0000 0x0 0x1000>;
551 interrupt-parent = <&gic>;
552 interrupts = <0 81 4>;
553 xlnx,bus-width = <64>;
554 #stream-id-cells = <1>;
555 iommus = <&smmu 0x86c>;
556 power-domains = <&pd_adma>;
559 lpd_dma_chan6: dma@ffad0000 {
561 compatible = "xlnx,zynqmp-dma-1.0";
562 clock-names = "clk_main", "clk_apb";
563 reg = <0x0 0xffad0000 0x0 0x1000>;
564 interrupt-parent = <&gic>;
565 interrupts = <0 82 4>;
566 xlnx,bus-width = <64>;
567 #stream-id-cells = <1>;
568 iommus = <&smmu 0x86d>;
569 power-domains = <&pd_adma>;
572 lpd_dma_chan7: dma@ffae0000 {
574 compatible = "xlnx,zynqmp-dma-1.0";
575 clock-names = "clk_main", "clk_apb";
576 reg = <0x0 0xffae0000 0x0 0x1000>;
577 interrupt-parent = <&gic>;
578 interrupts = <0 83 4>;
579 xlnx,bus-width = <64>;
580 #stream-id-cells = <1>;
581 iommus = <&smmu 0x86e>;
582 power-domains = <&pd_adma>;
585 lpd_dma_chan8: dma@ffaf0000 {
587 compatible = "xlnx,zynqmp-dma-1.0";
588 clock-names = "clk_main", "clk_apb";
589 reg = <0x0 0xffaf0000 0x0 0x1000>;
590 interrupt-parent = <&gic>;
591 interrupts = <0 84 4>;
592 xlnx,bus-width = <64>;
593 #stream-id-cells = <1>;
594 iommus = <&smmu 0x86f>;
595 power-domains = <&pd_adma>;
598 mc: memory-controller@fd070000 {
599 compatible = "xlnx,zynqmp-ddrc-2.40a";
600 reg = <0x0 0xfd070000 0x0 0x30000>;
601 interrupt-parent = <&gic>;
602 interrupts = <0 112 4>;
605 nand0: nand@ff100000 {
606 compatible = "arasan,nfc-v3p10";
608 reg = <0x0 0xff100000 0x0 0x1000>;
609 clock-names = "clk_sys", "clk_flash";
610 interrupt-parent = <&gic>;
611 interrupts = <0 14 4>;
612 #address-cells = <2>;
614 #stream-id-cells = <1>;
615 iommus = <&smmu 0x872>;
616 power-domains = <&pd_nand>;
619 gem0: ethernet@ff0b0000 {
620 compatible = "cdns,zynqmp-gem";
622 interrupt-parent = <&gic>;
623 interrupts = <0 57 4>, <0 57 4>;
624 reg = <0x0 0xff0b0000 0x0 0x1000>;
625 clock-names = "pclk", "hclk", "tx_clk";
626 #address-cells = <1>;
628 #stream-id-cells = <1>;
629 iommus = <&smmu 0x874>;
630 power-domains = <&pd_eth0>;
633 gem1: ethernet@ff0c0000 {
634 compatible = "cdns,zynqmp-gem";
636 interrupt-parent = <&gic>;
637 interrupts = <0 59 4>, <0 59 4>;
638 reg = <0x0 0xff0c0000 0x0 0x1000>;
639 clock-names = "pclk", "hclk", "tx_clk";
640 #address-cells = <1>;
642 #stream-id-cells = <1>;
643 iommus = <&smmu 0x875>;
644 power-domains = <&pd_eth1>;
647 gem2: ethernet@ff0d0000 {
648 compatible = "cdns,zynqmp-gem";
650 interrupt-parent = <&gic>;
651 interrupts = <0 61 4>, <0 61 4>;
652 reg = <0x0 0xff0d0000 0x0 0x1000>;
653 clock-names = "pclk", "hclk", "tx_clk";
654 #address-cells = <1>;
656 #stream-id-cells = <1>;
657 iommus = <&smmu 0x876>;
658 power-domains = <&pd_eth2>;
661 gem3: ethernet@ff0e0000 {
662 compatible = "cdns,zynqmp-gem";
664 interrupt-parent = <&gic>;
665 interrupts = <0 63 4>, <0 63 4>;
666 reg = <0x0 0xff0e0000 0x0 0x1000>;
667 clock-names = "pclk", "hclk", "tx_clk";
668 #address-cells = <1>;
670 #stream-id-cells = <1>;
671 iommus = <&smmu 0x877>;
672 power-domains = <&pd_eth3>;
675 gpio: gpio@ff0a0000 {
676 compatible = "xlnx,zynqmp-gpio-1.0";
679 interrupt-parent = <&gic>;
680 interrupts = <0 16 4>;
681 interrupt-controller;
682 #interrupt-cells = <2>;
683 reg = <0x0 0xff0a0000 0x0 0x1000>;
685 power-domains = <&pd_gpio>;
689 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
691 interrupt-parent = <&gic>;
692 interrupts = <0 17 4>;
693 reg = <0x0 0xff020000 0x0 0x1000>;
694 #address-cells = <1>;
696 power-domains = <&pd_i2c0>;
700 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
702 interrupt-parent = <&gic>;
703 interrupts = <0 18 4>;
704 reg = <0x0 0xff030000 0x0 0x1000>;
705 #address-cells = <1>;
707 power-domains = <&pd_i2c1>;
710 ocm: memory-controller@ff960000 {
711 compatible = "xlnx,zynqmp-ocmc-1.0";
712 reg = <0x0 0xff960000 0x0 0x1000>;
713 interrupt-parent = <&gic>;
714 interrupts = <0 10 4>;
717 pcie: pcie@fd0e0000 {
718 compatible = "xlnx,nwl-pcie-2.11";
720 #address-cells = <3>;
722 #interrupt-cells = <1>;
725 interrupt-parent = <&gic>;
726 interrupts = <0 118 4>,
729 <0 115 4>, /* MSI_1 [63...32] */
730 <0 114 4>; /* MSI_0 [31...0] */
731 interrupt-names = "misc","dummy","intx", "msi1", "msi0";
732 msi-parent = <&pcie>;
733 reg = <0x0 0xfd0e0000 0x0 0x1000>,
734 <0x0 0xfd480000 0x0 0x1000>,
735 <0x80 0x00000000 0x0 0x1000000>;
736 reg-names = "breg", "pcireg", "cfg";
737 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
738 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
739 bus-range = <0x00 0xff>;
740 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
741 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
742 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
743 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
744 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
745 power-domains = <&pd_pcie>;
746 pcie_intc: legacy-interrupt-controller {
747 interrupt-controller;
748 #address-cells = <0>;
749 #interrupt-cells = <1>;
754 compatible = "xlnx,zynqmp-qspi-1.0";
756 clock-names = "ref_clk", "pclk";
757 interrupts = <0 15 4>;
758 interrupt-parent = <&gic>;
760 reg = <0x0 0xff0f0000 0x0 0x1000>,
761 <0x0 0xc0000000 0x0 0x8000000>;
762 #address-cells = <1>;
764 #stream-id-cells = <1>;
765 iommus = <&smmu 0x873>;
766 power-domains = <&pd_qspi>;
770 compatible = "xlnx,zynqmp-rtc";
772 reg = <0x0 0xffa60000 0x0 0x100>;
773 interrupt-parent = <&gic>;
774 interrupts = <0 26 4>, <0 27 4>;
775 interrupt-names = "alarm", "sec";
776 calibration = <0x8000>;
779 serdes: zynqmp_phy@fd400000 {
780 compatible = "xlnx,zynqmp-psgtr";
782 reg = <0x0 0xfd400000 0x0 0x40000>,
783 <0x0 0xfd3d0000 0x0 0x1000>,
784 <0x0 0xfd1a0000 0x0 0x1000>,
785 <0x0 0xff5e0000 0x0 0x1000>;
786 reg-names = "serdes", "siou", "fpd", "lpd";
787 xlnx,tx_termination_fix;
802 sata: ahci@fd0c0000 {
803 compatible = "ceva,ahci-1v84";
805 reg = <0x0 0xfd0c0000 0x0 0x2000>;
806 interrupt-parent = <&gic>;
807 interrupts = <0 133 4>;
808 power-domains = <&pd_sata>;
809 #stream-id-cells = <4>;
810 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
811 <&smmu 0x4c2>, <&smmu 0x4c3>;
815 sdhci0: sdhci@ff160000 {
817 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
819 interrupt-parent = <&gic>;
820 interrupts = <0 48 4>;
821 reg = <0x0 0xff160000 0x0 0x1000>;
822 clock-names = "clk_xin", "clk_ahb";
823 xlnx,device_id = <0>;
824 #stream-id-cells = <1>;
825 iommus = <&smmu 0x870>;
826 power-domains = <&pd_sd0>;
829 sdhci1: sdhci@ff170000 {
831 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
833 interrupt-parent = <&gic>;
834 interrupts = <0 49 4>;
835 reg = <0x0 0xff170000 0x0 0x1000>;
836 clock-names = "clk_xin", "clk_ahb";
837 xlnx,device_id = <1>;
838 #stream-id-cells = <1>;
839 iommus = <&smmu 0x871>;
840 power-domains = <&pd_sd1>;
843 pinctrl0: pinctrl@ff180000 {
844 compatible = "xlnx,pinctrl-zynqmp";
846 reg = <0x0 0xff180000 0x0 0x1000>;
849 smmu: smmu@fd800000 {
850 compatible = "arm,mmu-500";
851 reg = <0x0 0xfd800000 0x0 0x20000>;
854 #global-interrupts = <1>;
855 interrupt-parent = <&gic>;
856 interrupts = <0 155 4>,
857 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
858 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
859 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
860 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
864 compatible = "cdns,spi-r1p6";
866 interrupt-parent = <&gic>;
867 interrupts = <0 19 4>;
868 reg = <0x0 0xff040000 0x0 0x1000>;
869 clock-names = "ref_clk", "pclk";
870 #address-cells = <1>;
872 power-domains = <&pd_spi0>;
876 compatible = "cdns,spi-r1p6";
878 interrupt-parent = <&gic>;
879 interrupts = <0 20 4>;
880 reg = <0x0 0xff050000 0x0 0x1000>;
881 clock-names = "ref_clk", "pclk";
882 #address-cells = <1>;
884 power-domains = <&pd_spi1>;
887 ttc0: timer@ff110000 {
888 compatible = "cdns,ttc";
890 interrupt-parent = <&gic>;
891 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
892 reg = <0x0 0xff110000 0x0 0x1000>;
894 power-domains = <&pd_ttc0>;
897 ttc1: timer@ff120000 {
898 compatible = "cdns,ttc";
900 interrupt-parent = <&gic>;
901 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
902 reg = <0x0 0xff120000 0x0 0x1000>;
904 power-domains = <&pd_ttc1>;
907 ttc2: timer@ff130000 {
908 compatible = "cdns,ttc";
910 interrupt-parent = <&gic>;
911 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
912 reg = <0x0 0xff130000 0x0 0x1000>;
914 power-domains = <&pd_ttc2>;
917 ttc3: timer@ff140000 {
918 compatible = "cdns,ttc";
920 interrupt-parent = <&gic>;
921 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
922 reg = <0x0 0xff140000 0x0 0x1000>;
924 power-domains = <&pd_ttc3>;
927 uart0: serial@ff000000 {
929 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
931 interrupt-parent = <&gic>;
932 interrupts = <0 21 4>;
933 reg = <0x0 0xff000000 0x0 0x1000>;
934 clock-names = "uart_clk", "pclk";
935 power-domains = <&pd_uart0>;
938 uart1: serial@ff010000 {
940 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
942 interrupt-parent = <&gic>;
943 interrupts = <0 22 4>;
944 reg = <0x0 0xff010000 0x0 0x1000>;
945 clock-names = "uart_clk", "pclk";
946 power-domains = <&pd_uart1>;
950 #address-cells = <2>;
953 compatible = "xlnx,zynqmp-dwc3";
954 clock-names = "bus_clk", "ref_clk";
955 clocks = <&clk125>, <&clk125>;
956 #stream-id-cells = <1>;
957 iommus = <&smmu 0x860>;
958 power-domains = <&pd_usb0>;
961 dwc3_0: dwc3@fe200000 {
962 compatible = "snps,dwc3";
964 reg = <0x0 0xfe200000 0x0 0x40000>;
965 interrupt-parent = <&gic>;
966 interrupts = <0 65 4>;
967 /* snps,quirk-frame-length-adjustment = <0x20>; */
973 #address-cells = <2>;
976 compatible = "xlnx,zynqmp-dwc3";
977 clock-names = "bus_clk", "ref_clk";
978 clocks = <&clk125>, <&clk125>;
979 #stream-id-cells = <1>;
980 iommus = <&smmu 0x861>;
981 power-domains = <&pd_usb1>;
984 dwc3_1: dwc3@fe300000 {
985 compatible = "snps,dwc3";
987 reg = <0x0 0xfe300000 0x0 0x40000>;
988 interrupt-parent = <&gic>;
989 interrupts = <0 70 4>;
990 /* snps,quirk-frame-length-adjustment = <0x20>; */
995 watchdog0: watchdog@fd4d0000 {
996 compatible = "cdns,wdt-r1p2";
998 interrupt-parent = <&gic>;
999 interrupts = <0 113 1>;
1000 reg = <0x0 0xfd4d0000 0x0 0x1000>;
1004 xilinx_drm: xilinx_drm {
1005 compatible = "xlnx,drm";
1006 status = "disabled";
1007 xlnx,encoder-slave = <&xlnx_dp>;
1008 xlnx,connector-type = "DisplayPort";
1009 xlnx,dp-sub = <&xlnx_dp_sub>;
1011 xlnx,pixel-format = "rgb565";
1013 dmas = <&xlnx_dpdma 3>;
1017 dmas = <&xlnx_dpdma 0>,
1020 dma-names = "dma0", "dma1", "dma2";
1025 xlnx_dp: dp@fd4a0000 {
1026 compatible = "xlnx,v-dp";
1027 status = "disabled";
1028 reg = <0x0 0xfd4a0000 0x0 0x1000>;
1029 interrupts = <0 119 4>;
1030 interrupt-parent = <&gic>;
1031 clock-names = "aclk", "aud_clk";
1032 power-domains = <&pd_dp>;
1033 xlnx,dp-version = "v1.2";
1034 xlnx,max-lanes = <2>;
1035 xlnx,max-link-rate = <540000>;
1036 xlnx,max-bpc = <16>;
1038 xlnx,colormetry = "rgb";
1040 xlnx,audio-chan = <2>;
1041 xlnx,dp-sub = <&xlnx_dp_sub>;
1042 xlnx,max-pclock-frequency = <300000>;
1045 xlnx_dp_snd_card: dp_snd_card {
1046 compatible = "xlnx,dp-snd-card";
1047 status = "disabled";
1048 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
1049 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
1052 xlnx_dp_snd_codec0: dp_snd_codec0 {
1053 compatible = "xlnx,dp-snd-codec";
1054 status = "disabled";
1055 clock-names = "aud_clk";
1058 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
1059 compatible = "xlnx,dp-snd-pcm";
1060 status = "disabled";
1061 dmas = <&xlnx_dpdma 4>;
1065 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1066 compatible = "xlnx,dp-snd-pcm";
1067 status = "disabled";
1068 dmas = <&xlnx_dpdma 5>;
1072 xlnx_dp_sub: dp_sub@fd4aa000 {
1073 compatible = "xlnx,dp-sub";
1074 status = "disabled";
1075 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1076 <0x0 0xfd4ab000 0x0 0x1000>,
1077 <0x0 0xfd4ac000 0x0 0x1000>;
1078 reg-names = "blend", "av_buf", "aud";
1079 xlnx,output-fmt = "rgb";
1080 xlnx,vid-fmt = "yuyv";
1081 xlnx,gfx-fmt = "rgb565";
1082 power-domains = <&pd_dp>;
1085 xlnx_dpdma: dma@fd4c0000 {
1086 compatible = "xlnx,dpdma";
1087 status = "disabled";
1088 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1089 interrupts = <0 122 4>;
1090 interrupt-parent = <&gic>;
1091 clock-names = "axi_clk";
1092 power-domains = <&pd_dp>;
1096 compatible = "xlnx,video0";
1099 compatible = "xlnx,video1";
1102 compatible = "xlnx,video2";
1104 dma-graphicschannel {
1105 compatible = "xlnx,graphics";
1108 compatible = "xlnx,audio0";
1111 compatible = "xlnx,audio1";