2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 compatible = "xlnx,zynqmp";
21 compatible = "arm,cortex-a53", "arm,armv8";
23 enable-method = "psci";
24 operating-points-v2 = <&cpu_opp_table>;
26 cpu-idle-states = <&CPU_SLEEP_0>;
30 compatible = "arm,cortex-a53", "arm,armv8";
32 enable-method = "psci";
34 operating-points-v2 = <&cpu_opp_table>;
35 cpu-idle-states = <&CPU_SLEEP_0>;
39 compatible = "arm,cortex-a53", "arm,armv8";
41 enable-method = "psci";
43 operating-points-v2 = <&cpu_opp_table>;
44 cpu-idle-states = <&CPU_SLEEP_0>;
48 compatible = "arm,cortex-a53", "arm,armv8";
50 enable-method = "psci";
52 operating-points-v2 = <&cpu_opp_table>;
53 cpu-idle-states = <&CPU_SLEEP_0>;
57 entry-method = "arm,psci";
59 CPU_SLEEP_0: cpu-sleep-0 {
60 compatible = "arm,idle-state";
61 arm,psci-suspend-param = <0x40000000>;
63 entry-latency-us = <300>;
64 exit-latency-us = <600>;
65 min-residency-us = <10000>;
70 cpu_opp_table: cpu_opp_table {
71 compatible = "operating-points-v2";
74 opp-hz = /bits/ 64 <1199999988>;
75 opp-microvolt = <1000000>;
76 clock-latency-ns = <500000>;
79 opp-hz = /bits/ 64 <599999994>;
80 opp-microvolt = <1000000>;
81 clock-latency-ns = <500000>;
84 opp-hz = /bits/ 64 <399999996>;
85 opp-microvolt = <1000000>;
86 clock-latency-ns = <500000>;
89 opp-hz = /bits/ 64 <299999997>;
90 opp-microvolt = <1000000>;
91 clock-latency-ns = <500000>;
96 compatible = "arm,dcc";
102 compatible = "xlnx,zynqmp-genpd";
105 #power-domain-cells = <0x0>;
110 #power-domain-cells = <0x0>;
115 #power-domain-cells = <0x0>;
120 #power-domain-cells = <0x0>;
125 #power-domain-cells = <0x0>;
130 #power-domain-cells = <0x0>;
135 #power-domain-cells = <0x0>;
140 #power-domain-cells = <0x0>;
145 #power-domain-cells = <0x0>;
150 #power-domain-cells = <0x0>;
155 #power-domain-cells = <0x0>;
160 #power-domain-cells = <0x0>;
165 #power-domain-cells = <0x0>;
170 /* fixme: what to attach to */
171 #power-domain-cells = <0x0>;
176 #power-domain-cells = <0x0>;
181 #power-domain-cells = <0x0>;
186 #power-domain-cells = <0x0>;
191 #power-domain-cells = <0x0>;
196 #power-domain-cells = <0x0>;
201 #power-domain-cells = <0x0>;
206 #power-domain-cells = <0x0>;
211 #power-domain-cells = <0x0>;
216 #power-domain-cells = <0x0>;
221 #power-domain-cells = <0x0>;
226 #power-domain-cells = <0x0>;
231 #power-domain-cells = <0x0>;
236 #power-domain-cells = <0x0>;
241 #power-domain-cells = <0x0>;
246 #power-domain-cells = <0x0>;
247 pd-id = <0x3a 0x14 0x15>;
252 compatible = "arm,armv8-pmuv3";
253 interrupt-parent = <&gic>;
254 interrupts = <0 143 4>,
261 compatible = "arm,psci-0.2";
266 compatible = "xlnx,zynqmp-pm";
268 interrupt-parent = <&gic>;
269 interrupts = <0 35 4>;
273 compatible = "arm,armv8-timer";
274 interrupt-parent = <&gic>;
275 interrupts = <1 13 0xf08>,
282 compatible = "arm,cortex-a53-edac";
285 fpga_full: fpga-full {
286 compatible = "fpga-region";
288 #address-cells = <2>;
293 compatible = "xlnx,zynqmp-pcap-fpga";
296 amba_apu: amba_apu@0 {
297 compatible = "simple-bus";
298 #address-cells = <2>;
300 ranges = <0 0 0 0 0xffffffff>;
302 gic: interrupt-controller@f9010000 {
303 compatible = "arm,gic-400", "arm,cortex-a15-gic";
304 #interrupt-cells = <3>;
305 reg = <0x0 0xf9010000 0x10000>,
306 <0x0 0xf9020000 0x20000>,
307 <0x0 0xf9040000 0x20000>,
308 <0x0 0xf9060000 0x20000>;
309 interrupt-controller;
310 interrupt-parent = <&gic>;
311 interrupts = <1 9 0xf04>;
316 compatible = "simple-bus";
318 #address-cells = <2>;
323 compatible = "xlnx,zynq-can-1.0";
325 clock-names = "can_clk", "pclk";
326 reg = <0x0 0xff060000 0x0 0x1000>;
327 interrupts = <0 23 4>;
328 interrupt-parent = <&gic>;
329 tx-fifo-depth = <0x40>;
330 rx-fifo-depth = <0x40>;
331 power-domains = <&pd_can0>;
335 compatible = "xlnx,zynq-can-1.0";
337 clock-names = "can_clk", "pclk";
338 reg = <0x0 0xff070000 0x0 0x1000>;
339 interrupts = <0 24 4>;
340 interrupt-parent = <&gic>;
341 tx-fifo-depth = <0x40>;
342 rx-fifo-depth = <0x40>;
343 power-domains = <&pd_can1>;
347 compatible = "arm,cci-400";
348 reg = <0x0 0xfd6e0000 0x0 0x9000>;
349 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
350 #address-cells = <1>;
354 compatible = "arm,cci-400-pmu,r1";
355 reg = <0x9000 0x5000>;
356 interrupt-parent = <&gic>;
357 interrupts = <0 123 4>,
366 fpd_dma_chan1: dma@fd500000 {
368 compatible = "xlnx,zynqmp-dma-1.0";
369 reg = <0x0 0xfd500000 0x0 0x1000>;
370 interrupt-parent = <&gic>;
371 interrupts = <0 124 4>;
372 clock-names = "clk_main", "clk_apb";
373 xlnx,bus-width = <128>;
374 #stream-id-cells = <1>;
375 iommus = <&smmu 0x14e8>;
376 power-domains = <&pd_gdma>;
379 fpd_dma_chan2: dma@fd510000 {
381 compatible = "xlnx,zynqmp-dma-1.0";
382 reg = <0x0 0xfd510000 0x0 0x1000>;
383 interrupt-parent = <&gic>;
384 interrupts = <0 125 4>;
385 clock-names = "clk_main", "clk_apb";
386 xlnx,bus-width = <128>;
387 #stream-id-cells = <1>;
388 iommus = <&smmu 0x14e9>;
389 power-domains = <&pd_gdma>;
392 fpd_dma_chan3: dma@fd520000 {
394 compatible = "xlnx,zynqmp-dma-1.0";
395 reg = <0x0 0xfd520000 0x0 0x1000>;
396 interrupt-parent = <&gic>;
397 interrupts = <0 126 4>;
398 clock-names = "clk_main", "clk_apb";
399 xlnx,bus-width = <128>;
400 #stream-id-cells = <1>;
401 iommus = <&smmu 0x14ea>;
402 power-domains = <&pd_gdma>;
405 fpd_dma_chan4: dma@fd530000 {
407 compatible = "xlnx,zynqmp-dma-1.0";
408 reg = <0x0 0xfd530000 0x0 0x1000>;
409 interrupt-parent = <&gic>;
410 interrupts = <0 127 4>;
411 clock-names = "clk_main", "clk_apb";
412 xlnx,bus-width = <128>;
413 #stream-id-cells = <1>;
414 iommus = <&smmu 0x14eb>;
415 power-domains = <&pd_gdma>;
418 fpd_dma_chan5: dma@fd540000 {
420 compatible = "xlnx,zynqmp-dma-1.0";
421 reg = <0x0 0xfd540000 0x0 0x1000>;
422 interrupt-parent = <&gic>;
423 interrupts = <0 128 4>;
424 clock-names = "clk_main", "clk_apb";
425 xlnx,bus-width = <128>;
426 #stream-id-cells = <1>;
427 iommus = <&smmu 0x14ec>;
428 power-domains = <&pd_gdma>;
431 fpd_dma_chan6: dma@fd550000 {
433 compatible = "xlnx,zynqmp-dma-1.0";
434 reg = <0x0 0xfd550000 0x0 0x1000>;
435 interrupt-parent = <&gic>;
436 interrupts = <0 129 4>;
437 clock-names = "clk_main", "clk_apb";
438 xlnx,bus-width = <128>;
439 #stream-id-cells = <1>;
440 iommus = <&smmu 0x14ed>;
441 power-domains = <&pd_gdma>;
444 fpd_dma_chan7: dma@fd560000 {
446 compatible = "xlnx,zynqmp-dma-1.0";
447 reg = <0x0 0xfd560000 0x0 0x1000>;
448 interrupt-parent = <&gic>;
449 interrupts = <0 130 4>;
450 clock-names = "clk_main", "clk_apb";
451 xlnx,bus-width = <128>;
452 #stream-id-cells = <1>;
453 iommus = <&smmu 0x14ee>;
454 power-domains = <&pd_gdma>;
457 fpd_dma_chan8: dma@fd570000 {
459 compatible = "xlnx,zynqmp-dma-1.0";
460 reg = <0x0 0xfd570000 0x0 0x1000>;
461 interrupt-parent = <&gic>;
462 interrupts = <0 131 4>;
463 clock-names = "clk_main", "clk_apb";
464 xlnx,bus-width = <128>;
465 #stream-id-cells = <1>;
466 iommus = <&smmu 0x14ef>;
467 power-domains = <&pd_gdma>;
472 compatible = "arm,mali-400", "arm,mali-utgard";
473 reg = <0x0 0xfd4b0000 0x0 0x10000>;
474 interrupt-parent = <&gic>;
475 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
476 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
477 clock-names = "gpu", "gpu_pp0", "gpu_pp1";
478 power-domains = <&pd_gpu>;
481 /* LPDDMA default allows only secured access. inorder to enable
482 * These dma channels, Users should ensure that these dma
483 * Channels are allowed for non secure access.
485 lpd_dma_chan1: dma@ffa80000 {
487 compatible = "xlnx,zynqmp-dma-1.0";
488 clock-names = "clk_main", "clk_apb";
489 reg = <0x0 0xffa80000 0x0 0x1000>;
490 interrupt-parent = <&gic>;
491 interrupts = <0 77 4>;
492 xlnx,bus-width = <64>;
493 #stream-id-cells = <1>;
494 iommus = <&smmu 0x868>;
495 power-domains = <&pd_adma>;
498 lpd_dma_chan2: dma@ffa90000 {
500 compatible = "xlnx,zynqmp-dma-1.0";
501 clock-names = "clk_main", "clk_apb";
502 reg = <0x0 0xffa90000 0x0 0x1000>;
503 interrupt-parent = <&gic>;
504 interrupts = <0 78 4>;
505 xlnx,bus-width = <64>;
506 #stream-id-cells = <1>;
507 iommus = <&smmu 0x869>;
508 power-domains = <&pd_adma>;
511 lpd_dma_chan3: dma@ffaa0000 {
513 compatible = "xlnx,zynqmp-dma-1.0";
514 clock-names = "clk_main", "clk_apb";
515 reg = <0x0 0xffaa0000 0x0 0x1000>;
516 interrupt-parent = <&gic>;
517 interrupts = <0 79 4>;
518 xlnx,bus-width = <64>;
519 #stream-id-cells = <1>;
520 iommus = <&smmu 0x86a>;
521 power-domains = <&pd_adma>;
524 lpd_dma_chan4: dma@ffab0000 {
526 compatible = "xlnx,zynqmp-dma-1.0";
527 clock-names = "clk_main", "clk_apb";
528 reg = <0x0 0xffab0000 0x0 0x1000>;
529 interrupt-parent = <&gic>;
530 interrupts = <0 80 4>;
531 xlnx,bus-width = <64>;
532 #stream-id-cells = <1>;
533 iommus = <&smmu 0x86b>;
534 power-domains = <&pd_adma>;
537 lpd_dma_chan5: dma@ffac0000 {
539 compatible = "xlnx,zynqmp-dma-1.0";
540 clock-names = "clk_main", "clk_apb";
541 reg = <0x0 0xffac0000 0x0 0x1000>;
542 interrupt-parent = <&gic>;
543 interrupts = <0 81 4>;
544 xlnx,bus-width = <64>;
545 #stream-id-cells = <1>;
546 iommus = <&smmu 0x86c>;
547 power-domains = <&pd_adma>;
550 lpd_dma_chan6: dma@ffad0000 {
552 compatible = "xlnx,zynqmp-dma-1.0";
553 clock-names = "clk_main", "clk_apb";
554 reg = <0x0 0xffad0000 0x0 0x1000>;
555 interrupt-parent = <&gic>;
556 interrupts = <0 82 4>;
557 xlnx,bus-width = <64>;
558 #stream-id-cells = <1>;
559 iommus = <&smmu 0x86d>;
560 power-domains = <&pd_adma>;
563 lpd_dma_chan7: dma@ffae0000 {
565 compatible = "xlnx,zynqmp-dma-1.0";
566 clock-names = "clk_main", "clk_apb";
567 reg = <0x0 0xffae0000 0x0 0x1000>;
568 interrupt-parent = <&gic>;
569 interrupts = <0 83 4>;
570 xlnx,bus-width = <64>;
571 #stream-id-cells = <1>;
572 iommus = <&smmu 0x86e>;
573 power-domains = <&pd_adma>;
576 lpd_dma_chan8: dma@ffaf0000 {
578 compatible = "xlnx,zynqmp-dma-1.0";
579 clock-names = "clk_main", "clk_apb";
580 reg = <0x0 0xffaf0000 0x0 0x1000>;
581 interrupt-parent = <&gic>;
582 interrupts = <0 84 4>;
583 xlnx,bus-width = <64>;
584 #stream-id-cells = <1>;
585 iommus = <&smmu 0x86f>;
586 power-domains = <&pd_adma>;
589 mc: memory-controller@fd070000 {
590 compatible = "xlnx,zynqmp-ddrc-2.40a";
591 reg = <0x0 0xfd070000 0x0 0x30000>;
592 interrupt-parent = <&gic>;
593 interrupts = <0 112 4>;
596 nand0: nand@ff100000 {
597 compatible = "arasan,nfc-v3p10";
599 reg = <0x0 0xff100000 0x0 0x1000>;
600 clock-names = "clk_sys", "clk_flash";
601 interrupt-parent = <&gic>;
602 interrupts = <0 14 4>;
603 #address-cells = <2>;
605 #stream-id-cells = <1>;
606 iommus = <&smmu 0x872>;
607 power-domains = <&pd_nand>;
610 gem0: ethernet@ff0b0000 {
611 compatible = "cdns,zynqmp-gem";
613 interrupt-parent = <&gic>;
614 interrupts = <0 57 4>, <0 57 4>;
615 reg = <0x0 0xff0b0000 0x0 0x1000>;
616 clock-names = "pclk", "hclk", "tx_clk";
617 #address-cells = <1>;
619 #stream-id-cells = <1>;
620 iommus = <&smmu 0x874>;
621 power-domains = <&pd_eth0>;
624 gem1: ethernet@ff0c0000 {
625 compatible = "cdns,zynqmp-gem";
627 interrupt-parent = <&gic>;
628 interrupts = <0 59 4>, <0 59 4>;
629 reg = <0x0 0xff0c0000 0x0 0x1000>;
630 clock-names = "pclk", "hclk", "tx_clk";
631 #address-cells = <1>;
633 #stream-id-cells = <1>;
634 iommus = <&smmu 0x875>;
635 power-domains = <&pd_eth1>;
638 gem2: ethernet@ff0d0000 {
639 compatible = "cdns,zynqmp-gem";
641 interrupt-parent = <&gic>;
642 interrupts = <0 61 4>, <0 61 4>;
643 reg = <0x0 0xff0d0000 0x0 0x1000>;
644 clock-names = "pclk", "hclk", "tx_clk";
645 #address-cells = <1>;
647 #stream-id-cells = <1>;
648 iommus = <&smmu 0x876>;
649 power-domains = <&pd_eth2>;
652 gem3: ethernet@ff0e0000 {
653 compatible = "cdns,zynqmp-gem";
655 interrupt-parent = <&gic>;
656 interrupts = <0 63 4>, <0 63 4>;
657 reg = <0x0 0xff0e0000 0x0 0x1000>;
658 clock-names = "pclk", "hclk", "tx_clk";
659 #address-cells = <1>;
661 #stream-id-cells = <1>;
662 iommus = <&smmu 0x877>;
663 power-domains = <&pd_eth3>;
666 gpio: gpio@ff0a0000 {
667 compatible = "xlnx,zynqmp-gpio-1.0";
670 interrupt-parent = <&gic>;
671 interrupts = <0 16 4>;
672 interrupt-controller;
673 #interrupt-cells = <2>;
674 reg = <0x0 0xff0a0000 0x0 0x1000>;
676 power-domains = <&pd_gpio>;
680 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
682 interrupt-parent = <&gic>;
683 interrupts = <0 17 4>;
684 reg = <0x0 0xff020000 0x0 0x1000>;
685 #address-cells = <1>;
687 power-domains = <&pd_i2c0>;
691 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
693 interrupt-parent = <&gic>;
694 interrupts = <0 18 4>;
695 reg = <0x0 0xff030000 0x0 0x1000>;
696 #address-cells = <1>;
698 power-domains = <&pd_i2c1>;
701 ocm: memory-controller@ff960000 {
702 compatible = "xlnx,zynqmp-ocmc-1.0";
703 reg = <0x0 0xff960000 0x0 0x1000>;
704 interrupt-parent = <&gic>;
705 interrupts = <0 10 4>;
708 pcie: pcie@fd0e0000 {
709 compatible = "xlnx,nwl-pcie-2.11";
711 #address-cells = <3>;
713 #interrupt-cells = <1>;
716 interrupt-parent = <&gic>;
717 interrupts = <0 118 4>,
720 <0 115 4>, /* MSI_1 [63...32] */
721 <0 114 4>; /* MSI_0 [31...0] */
722 interrupt-names = "misc","dummy","intx", "msi1", "msi0";
723 msi-parent = <&pcie>;
724 reg = <0x0 0xfd0e0000 0x0 0x1000>,
725 <0x0 0xfd480000 0x0 0x1000>,
726 <0x80 0x00000000 0x0 0x1000000>;
727 reg-names = "breg", "pcireg", "cfg";
728 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
729 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
730 bus-range = <0x00 0xff>;
731 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
732 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
733 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
734 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
735 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
736 power-domains = <&pd_pcie>;
737 pcie_intc: legacy-interrupt-controller {
738 interrupt-controller;
739 #address-cells = <0>;
740 #interrupt-cells = <1>;
745 compatible = "xlnx,zynqmp-qspi-1.0";
747 clock-names = "ref_clk", "pclk";
748 interrupts = <0 15 4>;
749 interrupt-parent = <&gic>;
751 reg = <0x0 0xff0f0000 0x0 0x1000>,
752 <0x0 0xc0000000 0x0 0x8000000>;
753 #address-cells = <1>;
755 #stream-id-cells = <1>;
756 iommus = <&smmu 0x873>;
757 power-domains = <&pd_qspi>;
761 compatible = "xlnx,zynqmp-rtc";
763 reg = <0x0 0xffa60000 0x0 0x100>;
764 interrupt-parent = <&gic>;
765 interrupts = <0 26 4>, <0 27 4>;
766 interrupt-names = "alarm", "sec";
769 serdes: zynqmp_phy@fd400000 {
770 compatible = "xlnx,zynqmp-psgtr";
772 reg = <0x0 0xfd400000 0x0 0x40000>,
773 <0x0 0xfd3d0000 0x0 0x1000>,
774 <0x0 0xfd1a0000 0x0 0x1000>,
775 <0x0 0xff5e0000 0x0 0x1000>;
776 reg-names = "serdes", "siou", "fpd", "lpd";
777 xlnx,tx_termination_fix;
792 sata: ahci@fd0c0000 {
793 compatible = "ceva,ahci-1v84";
795 reg = <0x0 0xfd0c0000 0x0 0x2000>;
796 interrupt-parent = <&gic>;
797 interrupts = <0 133 4>;
798 power-domains = <&pd_sata>;
801 sdhci0: sdhci@ff160000 {
803 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
805 interrupt-parent = <&gic>;
806 interrupts = <0 48 4>;
807 reg = <0x0 0xff160000 0x0 0x1000>;
808 clock-names = "clk_xin", "clk_ahb";
809 xlnx,device_id = <0>;
810 #stream-id-cells = <1>;
811 iommus = <&smmu 0x870>;
812 power-domains = <&pd_sd0>;
815 sdhci1: sdhci@ff170000 {
817 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
819 interrupt-parent = <&gic>;
820 interrupts = <0 49 4>;
821 reg = <0x0 0xff170000 0x0 0x1000>;
822 clock-names = "clk_xin", "clk_ahb";
823 xlnx,device_id = <1>;
824 #stream-id-cells = <1>;
825 iommus = <&smmu 0x871>;
826 power-domains = <&pd_sd1>;
829 smmu: smmu@fd800000 {
830 compatible = "arm,mmu-500";
831 reg = <0x0 0xfd800000 0x0 0x20000>;
833 #global-interrupts = <1>;
834 interrupt-parent = <&gic>;
835 interrupts = <0 155 4>,
836 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
837 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
838 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
839 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
840 mmu-masters = < &gem0 0x874
855 &fpd_dma_chan1 0x14e8
856 &fpd_dma_chan2 0x14e9
857 &fpd_dma_chan3 0x14ea
858 &fpd_dma_chan4 0x14eb
859 &fpd_dma_chan5 0x14ec
860 &fpd_dma_chan6 0x14ed
861 &fpd_dma_chan7 0x14ee
862 &fpd_dma_chan8 0x14ef
869 compatible = "cdns,spi-r1p6";
871 interrupt-parent = <&gic>;
872 interrupts = <0 19 4>;
873 reg = <0x0 0xff040000 0x0 0x1000>;
874 clock-names = "ref_clk", "pclk";
875 #address-cells = <1>;
877 power-domains = <&pd_spi0>;
881 compatible = "cdns,spi-r1p6";
883 interrupt-parent = <&gic>;
884 interrupts = <0 20 4>;
885 reg = <0x0 0xff050000 0x0 0x1000>;
886 clock-names = "ref_clk", "pclk";
887 #address-cells = <1>;
889 power-domains = <&pd_spi1>;
892 ttc0: timer@ff110000 {
893 compatible = "cdns,ttc";
895 interrupt-parent = <&gic>;
896 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
897 reg = <0x0 0xff110000 0x0 0x1000>;
899 power-domains = <&pd_ttc0>;
902 ttc1: timer@ff120000 {
903 compatible = "cdns,ttc";
905 interrupt-parent = <&gic>;
906 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
907 reg = <0x0 0xff120000 0x0 0x1000>;
909 power-domains = <&pd_ttc1>;
912 ttc2: timer@ff130000 {
913 compatible = "cdns,ttc";
915 interrupt-parent = <&gic>;
916 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
917 reg = <0x0 0xff130000 0x0 0x1000>;
919 power-domains = <&pd_ttc2>;
922 ttc3: timer@ff140000 {
923 compatible = "cdns,ttc";
925 interrupt-parent = <&gic>;
926 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
927 reg = <0x0 0xff140000 0x0 0x1000>;
929 power-domains = <&pd_ttc3>;
932 uart0: serial@ff000000 {
934 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
936 interrupt-parent = <&gic>;
937 interrupts = <0 21 4>;
938 reg = <0x0 0xff000000 0x0 0x1000>;
939 clock-names = "uart_clk", "pclk";
940 power-domains = <&pd_uart0>;
943 uart1: serial@ff010000 {
945 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
947 interrupt-parent = <&gic>;
948 interrupts = <0 22 4>;
949 reg = <0x0 0xff010000 0x0 0x1000>;
950 clock-names = "uart_clk", "pclk";
951 power-domains = <&pd_uart1>;
955 #address-cells = <2>;
958 compatible = "xlnx,zynqmp-dwc3";
959 clock-names = "bus_clk", "ref_clk";
960 clocks = <&clk125>, <&clk125>;
961 #stream-id-cells = <1>;
962 iommus = <&smmu 0x860>;
963 power-domains = <&pd_usb0>;
966 dwc3_0: dwc3@fe200000 {
967 compatible = "snps,dwc3";
969 reg = <0x0 0xfe200000 0x0 0x40000>;
970 interrupt-parent = <&gic>;
971 interrupts = <0 65 4>;
972 /* snps,quirk-frame-length-adjustment = <0x20>; */
978 #address-cells = <2>;
981 compatible = "xlnx,zynqmp-dwc3";
982 clock-names = "bus_clk", "ref_clk";
983 clocks = <&clk125>, <&clk125>;
984 #stream-id-cells = <1>;
985 iommus = <&smmu 0x861>;
986 power-domains = <&pd_usb1>;
989 dwc3_1: dwc3@fe300000 {
990 compatible = "snps,dwc3";
992 reg = <0x0 0xfe300000 0x0 0x40000>;
993 interrupt-parent = <&gic>;
994 interrupts = <0 70 4>;
995 /* snps,quirk-frame-length-adjustment = <0x20>; */
1000 watchdog0: watchdog@fd4d0000 {
1001 compatible = "cdns,wdt-r1p2";
1002 status = "disabled";
1003 interrupt-parent = <&gic>;
1004 interrupts = <0 113 1>;
1005 reg = <0x0 0xfd4d0000 0x0 0x1000>;
1009 xilinx_drm: xilinx_drm {
1010 compatible = "xlnx,drm";
1011 status = "disabled";
1012 xlnx,encoder-slave = <&xlnx_dp>;
1013 xlnx,connector-type = "DisplayPort";
1014 xlnx,dp-sub = <&xlnx_dp_sub>;
1016 xlnx,pixel-format = "rgb565";
1018 dmas = <&xlnx_dpdma 3>;
1022 dmas = <&xlnx_dpdma 0>,
1025 dma-names = "dma0", "dma1", "dma2";
1030 xlnx_dp: dp@fd4a0000 {
1031 compatible = "xlnx,v-dp";
1032 status = "disabled";
1033 reg = <0x0 0xfd4a0000 0x0 0x1000>;
1034 interrupts = <0 119 4>;
1035 interrupt-parent = <&gic>;
1036 clock-names = "aclk", "aud_clk";
1037 xlnx,dp-version = "v1.2";
1038 xlnx,max-lanes = <2>;
1039 xlnx,max-link-rate = <540000>;
1040 xlnx,max-bpc = <16>;
1042 xlnx,colormetry = "rgb";
1044 xlnx,audio-chan = <2>;
1045 xlnx,dp-sub = <&xlnx_dp_sub>;
1046 xlnx,max-pclock-frequency = <300000>;
1049 xlnx_dp_snd_card: dp_snd_card {
1050 compatible = "xlnx,dp-snd-card";
1051 status = "disabled";
1052 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
1053 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
1056 xlnx_dp_snd_codec0: dp_snd_codec0 {
1057 compatible = "xlnx,dp-snd-codec";
1058 status = "disabled";
1059 clock-names = "aud_clk";
1062 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
1063 compatible = "xlnx,dp-snd-pcm";
1064 status = "disabled";
1065 dmas = <&xlnx_dpdma 4>;
1069 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1070 compatible = "xlnx,dp-snd-pcm";
1071 status = "disabled";
1072 dmas = <&xlnx_dpdma 5>;
1076 xlnx_dp_sub: dp_sub@fd4aa000 {
1077 compatible = "xlnx,dp-sub";
1078 status = "disabled";
1079 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1080 <0x0 0xfd4ab000 0x0 0x1000>,
1081 <0x0 0xfd4ac000 0x0 0x1000>;
1082 reg-names = "blend", "av_buf", "aud";
1083 xlnx,output-fmt = "rgb";
1084 xlnx,vid-fmt = "yuyv";
1085 xlnx,gfx-fmt = "rgb565";
1088 xlnx_dpdma: dma@fd4c0000 {
1089 compatible = "xlnx,dpdma";
1090 status = "disabled";
1091 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1092 interrupts = <0 122 4>;
1093 interrupt-parent = <&gic>;
1094 clock-names = "axi_clk";
1098 compatible = "xlnx,video0";
1101 compatible = "xlnx,video1";
1104 compatible = "xlnx,video2";
1106 dma-graphicschannel {
1107 compatible = "xlnx,graphics";
1110 compatible = "xlnx,audio0";
1113 compatible = "xlnx,audio1";