arch/arm/dts/zynqmp.dtsi

   1 /*
   2  * dts file for Xilinx ZynqMP
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 / {
  12         compatible = "xlnx,zynqmp";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@0 {
  21                         compatible = "arm,cortex-a53", "arm,armv8";
  22                         device_type = "cpu";
  23                         enable-method = "psci";
  24                         operating-points-v2 = <&cpu_opp_table>;
  25                         reg = <0x0>;
  26                         cpu-idle-states = <&CPU_SLEEP_0>;
  27                 };
  28
  29                 cpu1: cpu@1 {
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         device_type = "cpu";
  32                         enable-method = "psci";
  33                         reg = <0x1>;
  34                         operating-points-v2 = <&cpu_opp_table>;
  35                         cpu-idle-states = <&CPU_SLEEP_0>;
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         device_type = "cpu";
  41                         enable-method = "psci";
  42                         reg = <0x2>;
  43                         operating-points-v2 = <&cpu_opp_table>;
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                 };
  46
  47                 cpu3: cpu@3 {
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         device_type = "cpu";
  50                         enable-method = "psci";
  51                         reg = <0x3>;
  52                         operating-points-v2 = <&cpu_opp_table>;
  53                         cpu-idle-states = <&CPU_SLEEP_0>;
  54                 };
  55
  56                 idle-states {
  57                         entry-method = "arm,psci";
  58
  59                         CPU_SLEEP_0: cpu-sleep-0 {
  60                                 compatible = "arm,idle-state";
  61                                 arm,psci-suspend-param = <0x40000000>;
  62                                 local-timer-stop;
  63                                 entry-latency-us = <300>;
  64                                 exit-latency-us = <600>;
  65                                 min-residency-us = <10000>;
  66                         };
  67                 };
  68         };
  69
  70         cpu_opp_table: cpu_opp_table {
  71                 compatible = "operating-points-v2";
  72                 opp-shared;
  73                 opp00 {
  74                         opp-hz = /bits/ 64 <1199999988>;
  75                         opp-microvolt = <1000000>;
  76                         clock-latency-ns = <500000>;
  77                 };
  78                 opp01 {
  79                         opp-hz = /bits/ 64 <599999994>;
  80                         opp-microvolt = <1000000>;
  81                         clock-latency-ns = <500000>;
  82                 };
  83                 opp02 {
  84                         opp-hz = /bits/ 64 <399999996>;
  85                         opp-microvolt = <1000000>;
  86                         clock-latency-ns = <500000>;
  87                 };
  88                 opp03 {
  89                         opp-hz = /bits/ 64 <299999997>;
  90                         opp-microvolt = <1000000>;
  91                         clock-latency-ns = <500000>;
  92                 };
  93         };
  94
  95         dcc: dcc {
  96                 compatible = "arm,dcc";
  97                 status = "disabled";
  98                 u-boot,dm-pre-reloc;
  99         };
 100
 101         power-domains {
 102                 compatible = "xlnx,zynqmp-genpd";
 103
 104                 pd_usb0: pd-usb0 {
 105                         #power-domain-cells = <0x0>;
 106                         pd-id = <0x16>;
 107                 };
 108
 109                 pd_usb1: pd-usb1 {
 110                         #power-domain-cells = <0x0>;
 111                         pd-id = <0x17>;
 112                 };
 113
 114                 pd_sata: pd-sata {
 115                         #power-domain-cells = <0x0>;
 116                         pd-id = <0x1c>;
 117                 };
 118
 119                 pd_spi0: pd-spi0 {
 120                         #power-domain-cells = <0x0>;
 121                         pd-id = <0x23>;
 122                 };
 123
 124                 pd_spi1: pd-spi1 {
 125                         #power-domain-cells = <0x0>;
 126                         pd-id = <0x24>;
 127                 };
 128
 129                 pd_uart0: pd-uart0 {
 130                         #power-domain-cells = <0x0>;
 131                         pd-id = <0x21>;
 132                 };
 133
 134                 pd_uart1: pd-uart1 {
 135                         #power-domain-cells = <0x0>;
 136                         pd-id = <0x22>;
 137                 };
 138
 139                 pd_eth0: pd-eth0 {
 140                         #power-domain-cells = <0x0>;
 141                         pd-id = <0x1d>;
 142                 };
 143
 144                 pd_eth1: pd-eth1 {
 145                         #power-domain-cells = <0x0>;
 146                         pd-id = <0x1e>;
 147                 };
 148
 149                 pd_eth2: pd-eth2 {
 150                         #power-domain-cells = <0x0>;
 151                         pd-id = <0x1f>;
 152                 };
 153
 154                 pd_eth3: pd-eth3 {
 155                         #power-domain-cells = <0x0>;
 156                         pd-id = <0x20>;
 157                 };
 158
 159                 pd_i2c0: pd-i2c0 {
 160                         #power-domain-cells = <0x0>;
 161                         pd-id = <0x25>;
 162                 };
 163
 164                 pd_i2c1: pd-i2c1 {
 165                         #power-domain-cells = <0x0>;
 166                         pd-id = <0x26>;
 167                 };
 168
 169                 pd_dp: pd-dp {
 170                         /* fixme: what to attach to */
 171                         #power-domain-cells = <0x0>;
 172                         pd-id = <0x29>;
 173                 };
 174
 175                 pd_gdma: pd-gdma {
 176                         #power-domain-cells = <0x0>;
 177                         pd-id = <0x2a>;
 178                 };
 179
 180                 pd_adma: pd-adma {
 181                         #power-domain-cells = <0x0>;
 182                         pd-id = <0x2b>;
 183                 };
 184
 185                 pd_ttc0: pd-ttc0 {
 186                         #power-domain-cells = <0x0>;
 187                         pd-id = <0x18>;
 188                 };
 189
 190                 pd_ttc1: pd-ttc1 {
 191                         #power-domain-cells = <0x0>;
 192                         pd-id = <0x19>;
 193                 };
 194
 195                 pd_ttc2: pd-ttc2 {
 196                         #power-domain-cells = <0x0>;
 197                         pd-id = <0x1a>;
 198                 };
 199
 200                 pd_ttc3: pd-ttc3 {
 201                         #power-domain-cells = <0x0>;
 202                         pd-id = <0x1b>;
 203                 };
 204
 205                 pd_sd0: pd-sd0 {
 206                         #power-domain-cells = <0x0>;
 207                         pd-id = <0x27>;
 208                 };
 209
 210                 pd_sd1: pd-sd1 {
 211                         #power-domain-cells = <0x0>;
 212                         pd-id = <0x28>;
 213                 };
 214
 215                 pd_nand: pd-nand {
 216                         #power-domain-cells = <0x0>;
 217                         pd-id = <0x2c>;
 218                 };
 219
 220                 pd_qspi: pd-qspi {
 221                         #power-domain-cells = <0x0>;
 222                         pd-id = <0x2d>;
 223                 };
 224
 225                 pd_gpio: pd-gpio {
 226                         #power-domain-cells = <0x0>;
 227                         pd-id = <0x2e>;
 228                 };
 229
 230                 pd_can0: pd-can0 {
 231                         #power-domain-cells = <0x0>;
 232                         pd-id = <0x2f>;
 233                 };
 234
 235                 pd_can1: pd-can1 {
 236                         #power-domain-cells = <0x0>;
 237                         pd-id = <0x30>;
 238                 };
 239
 240                 pd_pcie: pd-pcie {
 241                         #power-domain-cells = <0x0>;
 242                         pd-id = <0x3b>;
 243                 };
 244
 245                 pd_gpu: pd-gpu {
 246                         #power-domain-cells = <0x0>;
 247                         pd-id = <0x3a 0x14 0x15>;
 248                 };
 249         };
 250
 251         pmu {
 252                 compatible = "arm,armv8-pmuv3";
 253                 interrupt-parent = <&gic>;
 254                 interrupts = <0 143 4>,
 255                              <0 144 4>,
 256                              <0 145 4>,
 257                              <0 146 4>;
 258         };
 259
 260         psci {
 261                 compatible = "arm,psci-0.2";
 262                 method = "smc";
 263         };
 264
 265         firmware {
 266                 compatible = "xlnx,zynqmp-pm";
 267                 method = "smc";
 268                 interrupt-parent = <&gic>;
 269                 interrupts = <0 35 4>;
 270         };
 271
 272         timer {
 273                 compatible = "arm,armv8-timer";
 274                 interrupt-parent = <&gic>;
 275                 interrupts = <1 13 0xf08>,
 276                              <1 14 0xf08>,
 277                              <1 11 0xf08>,
 278                              <1 10 0xf08>;
 279         };
 280
 281         edac {
 282                 compatible = "arm,cortex-a53-edac";
 283         };
 284
 285         fpga_full: fpga-full {
 286                 compatible = "fpga-region";
 287                 fpga-mgr = <&pcap>;
 288                 #address-cells = <2>;
 289                 #size-cells = <2>;
 290         };
 291
 292         pcap: pcap {
 293                 compatible = "xlnx,zynqmp-pcap-fpga";
 294         };
 295
 296         amba_apu: amba_apu@0 {
 297                 compatible = "simple-bus";
 298                 #address-cells = <2>;
 299                 #size-cells = <1>;
 300                 ranges = <0 0 0 0 0xffffffff>;
 301
 302                 gic: interrupt-controller@f9010000 {
 303                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
 304                         #interrupt-cells = <3>;
 305                         reg = <0x0 0xf9010000 0x10000>,
 306                               <0x0 0xf9020000 0x20000>,
 307                               <0x0 0xf9040000 0x20000>,
 308                               <0x0 0xf9060000 0x20000>;
 309                         interrupt-controller;
 310                         interrupt-parent = <&gic>;
 311                         interrupts = <1 9 0xf04>;
 312                 };
 313         };
 314
 315         amba: amba {
 316                 compatible = "simple-bus";
 317                 u-boot,dm-pre-reloc;
 318                 #address-cells = <2>;
 319                 #size-cells = <2>;
 320                 ranges;
 321
 322                 can0: can@ff060000 {
 323                         compatible = "xlnx,zynq-can-1.0";
 324                         status = "disabled";
 325                         clock-names = "can_clk", "pclk";
 326                         reg = <0x0 0xff060000 0x0 0x1000>;
 327                         interrupts = <0 23 4>;
 328                         interrupt-parent = <&gic>;
 329                         tx-fifo-depth = <0x40>;
 330                         rx-fifo-depth = <0x40>;
 331                         power-domains = <&pd_can0>;
 332                 };
 333
 334                 can1: can@ff070000 {
 335                         compatible = "xlnx,zynq-can-1.0";
 336                         status = "disabled";
 337                         clock-names = "can_clk", "pclk";
 338                         reg = <0x0 0xff070000 0x0 0x1000>;
 339                         interrupts = <0 24 4>;
 340                         interrupt-parent = <&gic>;
 341                         tx-fifo-depth = <0x40>;
 342                         rx-fifo-depth = <0x40>;
 343                         power-domains = <&pd_can1>;
 344                 };
 345
 346                 cci: cci@fd6e0000 {
 347                         compatible = "arm,cci-400";
 348                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 349                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 350                         #address-cells = <1>;
 351                         #size-cells = <1>;
 352
 353                         pmu@9000 {
 354                                 compatible = "arm,cci-400-pmu,r1";
 355                                 reg = <0x9000 0x5000>;
 356                                 interrupt-parent = <&gic>;
 357                                 interrupts = <0 123 4>,
 358                                              <0 123 4>,
 359                                              <0 123 4>,
 360                                              <0 123 4>,
 361                                              <0 123 4>;
 362                         };
 363                 };
 364
 365                 /* GDMA */
 366                 fpd_dma_chan1: dma@fd500000 {
 367                         status = "disabled";
 368                         compatible = "xlnx,zynqmp-dma-1.0";
 369                         reg = <0x0 0xfd500000 0x0 0x1000>;
 370                         interrupt-parent = <&gic>;
 371                         interrupts = <0 124 4>;
 372                         clock-names = "clk_main", "clk_apb";
 373                         xlnx,bus-width = <128>;
 374                         #stream-id-cells = <1>;
 375                         iommus = <&smmu 0x14e8>;
 376                         power-domains = <&pd_gdma>;
 377                 };
 378
 379                 fpd_dma_chan2: dma@fd510000 {
 380                         status = "disabled";
 381                         compatible = "xlnx,zynqmp-dma-1.0";
 382                         reg = <0x0 0xfd510000 0x0 0x1000>;
 383                         interrupt-parent = <&gic>;
 384                         interrupts = <0 125 4>;
 385                         clock-names = "clk_main", "clk_apb";
 386                         xlnx,bus-width = <128>;
 387                         #stream-id-cells = <1>;
 388                         iommus = <&smmu 0x14e9>;
 389                         power-domains = <&pd_gdma>;
 390                 };
 391
 392                 fpd_dma_chan3: dma@fd520000 {
 393                         status = "disabled";
 394                         compatible = "xlnx,zynqmp-dma-1.0";
 395                         reg = <0x0 0xfd520000 0x0 0x1000>;
 396                         interrupt-parent = <&gic>;
 397                         interrupts = <0 126 4>;
 398                         clock-names = "clk_main", "clk_apb";
 399                         xlnx,bus-width = <128>;
 400                         #stream-id-cells = <1>;
 401                         iommus = <&smmu 0x14ea>;
 402                         power-domains = <&pd_gdma>;
 403                 };
 404
 405                 fpd_dma_chan4: dma@fd530000 {
 406                         status = "disabled";
 407                         compatible = "xlnx,zynqmp-dma-1.0";
 408                         reg = <0x0 0xfd530000 0x0 0x1000>;
 409                         interrupt-parent = <&gic>;
 410                         interrupts = <0 127 4>;
 411                         clock-names = "clk_main", "clk_apb";
 412                         xlnx,bus-width = <128>;
 413                         #stream-id-cells = <1>;
 414                         iommus = <&smmu 0x14eb>;
 415                         power-domains = <&pd_gdma>;
 416                 };
 417
 418                 fpd_dma_chan5: dma@fd540000 {
 419                         status = "disabled";
 420                         compatible = "xlnx,zynqmp-dma-1.0";
 421                         reg = <0x0 0xfd540000 0x0 0x1000>;
 422                         interrupt-parent = <&gic>;
 423                         interrupts = <0 128 4>;
 424                         clock-names = "clk_main", "clk_apb";
 425                         xlnx,bus-width = <128>;
 426                         #stream-id-cells = <1>;
 427                         iommus = <&smmu 0x14ec>;
 428                         power-domains = <&pd_gdma>;
 429                 };
 430
 431                 fpd_dma_chan6: dma@fd550000 {
 432                         status = "disabled";
 433                         compatible = "xlnx,zynqmp-dma-1.0";
 434                         reg = <0x0 0xfd550000 0x0 0x1000>;
 435                         interrupt-parent = <&gic>;
 436                         interrupts = <0 129 4>;
 437                         clock-names = "clk_main", "clk_apb";
 438                         xlnx,bus-width = <128>;
 439                         #stream-id-cells = <1>;
 440                         iommus = <&smmu 0x14ed>;
 441                         power-domains = <&pd_gdma>;
 442                 };
 443
 444                 fpd_dma_chan7: dma@fd560000 {
 445                         status = "disabled";
 446                         compatible = "xlnx,zynqmp-dma-1.0";
 447                         reg = <0x0 0xfd560000 0x0 0x1000>;
 448                         interrupt-parent = <&gic>;
 449                         interrupts = <0 130 4>;
 450                         clock-names = "clk_main", "clk_apb";
 451                         xlnx,bus-width = <128>;
 452                         #stream-id-cells = <1>;
 453                         iommus = <&smmu 0x14ee>;
 454                         power-domains = <&pd_gdma>;
 455                 };
 456
 457                 fpd_dma_chan8: dma@fd570000 {
 458                         status = "disabled";
 459                         compatible = "xlnx,zynqmp-dma-1.0";
 460                         reg = <0x0 0xfd570000 0x0 0x1000>;
 461                         interrupt-parent = <&gic>;
 462                         interrupts = <0 131 4>;
 463                         clock-names = "clk_main", "clk_apb";
 464                         xlnx,bus-width = <128>;
 465                         #stream-id-cells = <1>;
 466                         iommus = <&smmu 0x14ef>;
 467                         power-domains = <&pd_gdma>;
 468                 };
 469
 470                 gpu: gpu@fd4b0000 {
 471                         status = "disabled";
 472                         compatible = "arm,mali-400", "arm,mali-utgard";
 473                         reg = <0x0 0xfd4b0000 0x0 0x30000>;
 474                         interrupt-parent = <&gic>;
 475                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 476                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 477                         clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 478                         power-domains = <&pd_gpu>;
 479                 };
 480
 481                 /* LPDDMA default allows only secured access. inorder to enable
 482                  * These dma channels, Users should ensure that these dma
 483                  * Channels are allowed for non secure access.
 484                  */
 485                 lpd_dma_chan1: dma@ffa80000 {
 486                         status = "disabled";
 487                         compatible = "xlnx,zynqmp-dma-1.0";
 488                         clock-names = "clk_main", "clk_apb";
 489                         reg = <0x0 0xffa80000 0x0 0x1000>;
 490                         interrupt-parent = <&gic>;
 491                         interrupts = <0 77 4>;
 492                         xlnx,bus-width = <64>;
 493                         #stream-id-cells = <1>;
 494                         iommus = <&smmu 0x868>;
 495                         power-domains = <&pd_adma>;
 496                 };
 497
 498                 lpd_dma_chan2: dma@ffa90000 {
 499                         status = "disabled";
 500                         compatible = "xlnx,zynqmp-dma-1.0";
 501                         clock-names = "clk_main", "clk_apb";
 502                         reg = <0x0 0xffa90000 0x0 0x1000>;
 503                         interrupt-parent = <&gic>;
 504                         interrupts = <0 78 4>;
 505                         xlnx,bus-width = <64>;
 506                         #stream-id-cells = <1>;
 507                         iommus = <&smmu 0x869>;
 508                         power-domains = <&pd_adma>;
 509                 };
 510
 511                 lpd_dma_chan3: dma@ffaa0000 {
 512                         status = "disabled";
 513                         compatible = "xlnx,zynqmp-dma-1.0";
 514                         clock-names = "clk_main", "clk_apb";
 515                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 516                         interrupt-parent = <&gic>;
 517                         interrupts = <0 79 4>;
 518                         xlnx,bus-width = <64>;
 519                         #stream-id-cells = <1>;
 520                         iommus = <&smmu 0x86a>;
 521                         power-domains = <&pd_adma>;
 522                 };
 523
 524                 lpd_dma_chan4: dma@ffab0000 {
 525                         status = "disabled";
 526                         compatible = "xlnx,zynqmp-dma-1.0";
 527                         clock-names = "clk_main", "clk_apb";
 528                         reg = <0x0 0xffab0000 0x0 0x1000>;
 529                         interrupt-parent = <&gic>;
 530                         interrupts = <0 80 4>;
 531                         xlnx,bus-width = <64>;
 532                         #stream-id-cells = <1>;
 533                         iommus = <&smmu 0x86b>;
 534                         power-domains = <&pd_adma>;
 535                 };
 536
 537                 lpd_dma_chan5: dma@ffac0000 {
 538                         status = "disabled";
 539                         compatible = "xlnx,zynqmp-dma-1.0";
 540                         clock-names = "clk_main", "clk_apb";
 541                         reg = <0x0 0xffac0000 0x0 0x1000>;
 542                         interrupt-parent = <&gic>;
 543                         interrupts = <0 81 4>;
 544                         xlnx,bus-width = <64>;
 545                         #stream-id-cells = <1>;
 546                         iommus = <&smmu 0x86c>;
 547                         power-domains = <&pd_adma>;
 548                 };
 549
 550                 lpd_dma_chan6: dma@ffad0000 {
 551                         status = "disabled";
 552                         compatible = "xlnx,zynqmp-dma-1.0";
 553                         clock-names = "clk_main", "clk_apb";
 554                         reg = <0x0 0xffad0000 0x0 0x1000>;
 555                         interrupt-parent = <&gic>;
 556                         interrupts = <0 82 4>;
 557                         xlnx,bus-width = <64>;
 558                         #stream-id-cells = <1>;
 559                         iommus = <&smmu 0x86d>;
 560                         power-domains = <&pd_adma>;
 561                 };
 562
 563                 lpd_dma_chan7: dma@ffae0000 {
 564                         status = "disabled";
 565                         compatible = "xlnx,zynqmp-dma-1.0";
 566                         clock-names = "clk_main", "clk_apb";
 567                         reg = <0x0 0xffae0000 0x0 0x1000>;
 568                         interrupt-parent = <&gic>;
 569                         interrupts = <0 83 4>;
 570                         xlnx,bus-width = <64>;
 571                         #stream-id-cells = <1>;
 572                         iommus = <&smmu 0x86e>;
 573                         power-domains = <&pd_adma>;
 574                 };
 575
 576                 lpd_dma_chan8: dma@ffaf0000 {
 577                         status = "disabled";
 578                         compatible = "xlnx,zynqmp-dma-1.0";
 579                         clock-names = "clk_main", "clk_apb";
 580                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 581                         interrupt-parent = <&gic>;
 582                         interrupts = <0 84 4>;
 583                         xlnx,bus-width = <64>;
 584                         #stream-id-cells = <1>;
 585                         iommus = <&smmu 0x86f>;
 586                         power-domains = <&pd_adma>;
 587                 };
 588
 589                 mc: memory-controller@fd070000 {
 590                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 591                         reg = <0x0 0xfd070000 0x0 0x30000>;
 592                         interrupt-parent = <&gic>;
 593                         interrupts = <0 112 4>;
 594                 };
 595
 596                 nand0: nand@ff100000 {
 597                         compatible = "arasan,nfc-v3p10";
 598                         status = "disabled";
 599                         reg = <0x0 0xff100000 0x0 0x1000>;
 600                         clock-names = "clk_sys", "clk_flash";
 601                         interrupt-parent = <&gic>;
 602                         interrupts = <0 14 4>;
 603                         #address-cells = <2>;
 604                         #size-cells = <1>;
 605                         #stream-id-cells = <1>;
 606                         iommus = <&smmu 0x872>;
 607                         power-domains = <&pd_nand>;
 608                 };
 609
 610                 gem0: ethernet@ff0b0000 {
 611                         compatible = "cdns,zynqmp-gem";
 612                         status = "disabled";
 613                         interrupt-parent = <&gic>;
 614                         interrupts = <0 57 4>, <0 57 4>;
 615                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 616                         clock-names = "pclk", "hclk", "tx_clk";
 617                         #address-cells = <1>;
 618                         #size-cells = <0>;
 619                         #stream-id-cells = <1>;
 620                         iommus = <&smmu 0x874>;
 621                         power-domains = <&pd_eth0>;
 622                 };
 623
 624                 gem1: ethernet@ff0c0000 {
 625                         compatible = "cdns,zynqmp-gem";
 626                         status = "disabled";
 627                         interrupt-parent = <&gic>;
 628                         interrupts = <0 59 4>, <0 59 4>;
 629                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 630                         clock-names = "pclk", "hclk", "tx_clk";
 631                         #address-cells = <1>;
 632                         #size-cells = <0>;
 633                         #stream-id-cells = <1>;
 634                         iommus = <&smmu 0x875>;
 635                         power-domains = <&pd_eth1>;
 636                 };
 637
 638                 gem2: ethernet@ff0d0000 {
 639                         compatible = "cdns,zynqmp-gem";
 640                         status = "disabled";
 641                         interrupt-parent = <&gic>;
 642                         interrupts = <0 61 4>, <0 61 4>;
 643                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 644                         clock-names = "pclk", "hclk", "tx_clk";
 645                         #address-cells = <1>;
 646                         #size-cells = <0>;
 647                         #stream-id-cells = <1>;
 648                         iommus = <&smmu 0x876>;
 649                         power-domains = <&pd_eth2>;
 650                 };
 651
 652                 gem3: ethernet@ff0e0000 {
 653                         compatible = "cdns,zynqmp-gem";
 654                         status = "disabled";
 655                         interrupt-parent = <&gic>;
 656                         interrupts = <0 63 4>, <0 63 4>;
 657                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 658                         clock-names = "pclk", "hclk", "tx_clk";
 659                         #address-cells = <1>;
 660                         #size-cells = <0>;
 661                         #stream-id-cells = <1>;
 662                         iommus = <&smmu 0x877>;
 663                         power-domains = <&pd_eth3>;
 664                 };
 665
 666                 gpio: gpio@ff0a0000 {
 667                         compatible = "xlnx,zynqmp-gpio-1.0";
 668                         status = "disabled";
 669                         #gpio-cells = <0x2>;
 670                         interrupt-parent = <&gic>;
 671                         interrupts = <0 16 4>;
 672                         interrupt-controller;
 673                         #interrupt-cells = <2>;
 674                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 675                         power-domains = <&pd_gpio>;
 676                 };
 677
 678                 i2c0: i2c@ff020000 {
 679                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 680                         status = "disabled";
 681                         interrupt-parent = <&gic>;
 682                         interrupts = <0 17 4>;
 683                         reg = <0x0 0xff020000 0x0 0x1000>;
 684                         #address-cells = <1>;
 685                         #size-cells = <0>;
 686                         power-domains = <&pd_i2c0>;
 687                 };
 688
 689                 i2c1: i2c@ff030000 {
 690                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 691                         status = "disabled";
 692                         interrupt-parent = <&gic>;
 693                         interrupts = <0 18 4>;
 694                         reg = <0x0 0xff030000 0x0 0x1000>;
 695                         #address-cells = <1>;
 696                         #size-cells = <0>;
 697                         power-domains = <&pd_i2c1>;
 698                 };
 699
 700                 ocm: memory-controller@ff960000 {
 701                         compatible = "xlnx,zynqmp-ocmc-1.0";
 702                         reg = <0x0 0xff960000 0x0 0x1000>;
 703                         interrupt-parent = <&gic>;
 704                         interrupts = <0 10 4>;
 705                 };
 706
 707                 pcie: pcie@fd0e0000 {
 708                         compatible = "xlnx,nwl-pcie-2.11";
 709                         status = "disabled";
 710                         #address-cells = <3>;
 711                         #size-cells = <2>;
 712                         #interrupt-cells = <1>;
 713                         msi-controller;
 714                         device_type = "pci";
 715                         interrupt-parent = <&gic>;
 716                         interrupts = <0 118 4>,
 717                                      <0 117 4>,
 718                                      <0 116 4>,
 719                                      <0 115 4>, /* MSI_1 [63...32] */
 720                                      <0 114 4>; /* MSI_0 [31...0] */
 721                         interrupt-names = "misc","dummy","intx", "msi1", "msi0";
 722                         msi-parent = <&pcie>;
 723                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 724                               <0x0 0xfd480000 0x0 0x1000>,
 725                               <0x80 0x00000000 0x0 0x1000000>;
 726                         reg-names = "breg", "pcireg", "cfg";
 727                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 728                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 729                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 730                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 731                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 732                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 733                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 734                         power-domains = <&pd_pcie>;
 735                         pcie_intc: legacy-interrupt-controller {
 736                                 interrupt-controller;
 737                                 #address-cells = <0>;
 738                                 #interrupt-cells = <1>;
 739                         };
 740                 };
 741
 742                 qspi: spi@ff0f0000 {
 743                         compatible = "xlnx,zynqmp-qspi-1.0";
 744                         status = "disabled";
 745                         clock-names = "ref_clk", "pclk";
 746                         interrupts = <0 15 4>;
 747                         interrupt-parent = <&gic>;
 748                         num-cs = <1>;
 749                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 750                               <0x0 0xc0000000 0x0 0x8000000>;
 751                         #address-cells = <1>;
 752                         #size-cells = <0>;
 753                         #stream-id-cells = <1>;
 754                         iommus = <&smmu 0x873>;
 755                         power-domains = <&pd_qspi>;
 756                 };
 757
 758                 rtc: rtc@ffa60000 {
 759                         compatible = "xlnx,zynqmp-rtc";
 760                         status = "disabled";
 761                         reg = <0x0 0xffa60000 0x0 0x100>;
 762                         interrupt-parent = <&gic>;
 763                         interrupts = <0 26 4>, <0 27 4>;
 764                         interrupt-names = "alarm", "sec";
 765                 };
 766
 767                 serdes: zynqmp_phy@fd400000 {
 768                         compatible = "xlnx,zynqmp-psgtr";
 769                         status = "disabled";
 770                         reg = <0x0 0xfd400000 0x0 0x40000>,
 771                               <0x0 0xfd3d0000 0x0 0x1000>,
 772                               <0x0 0xfd1a0000 0x0 0x1000>,
 773                               <0x0 0xff5e0000 0x0 0x1000>;
 774                         reg-names = "serdes", "siou", "fpd", "lpd";
 775                         xlnx,tx_termination_fix;
 776                         lane0: lane0 {
 777                                 #phy-cells = <4>;
 778                         };
 779                         lane1: lane1 {
 780                                 #phy-cells = <4>;
 781                         };
 782                         lane2: lane2 {
 783                                 #phy-cells = <4>;
 784                         };
 785                         lane3: lane3 {
 786                                 #phy-cells = <4>;
 787                         };
 788                 };
 789
 790                 sata: ahci@fd0c0000 {
 791                         compatible = "ceva,ahci-1v84";
 792                         status = "disabled";
 793                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 794                         interrupt-parent = <&gic>;
 795                         interrupts = <0 133 4>;
 796                         power-domains = <&pd_sata>;
 797                 };
 798
 799                 sdhci0: sdhci@ff160000 {
 800                         u-boot,dm-pre-reloc;
 801                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 802                         status = "disabled";
 803                         interrupt-parent = <&gic>;
 804                         interrupts = <0 48 4>;
 805                         reg = <0x0 0xff160000 0x0 0x1000>;
 806                         clock-names = "clk_xin", "clk_ahb";
 807                         xlnx,device_id = <0>;
 808                         #stream-id-cells = <1>;
 809                         iommus = <&smmu 0x870>;
 810                         power-domains = <&pd_sd0>;
 811                 };
 812
 813                 sdhci1: sdhci@ff170000 {
 814                         u-boot,dm-pre-reloc;
 815                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 816                         status = "disabled";
 817                         interrupt-parent = <&gic>;
 818                         interrupts = <0 49 4>;
 819                         reg = <0x0 0xff170000 0x0 0x1000>;
 820                         clock-names = "clk_xin", "clk_ahb";
 821                         xlnx,device_id = <1>;
 822                         #stream-id-cells = <1>;
 823                         iommus = <&smmu 0x871>;
 824                         power-domains = <&pd_sd1>;
 825                 };
 826
 827                 smmu: smmu@fd800000 {
 828                         compatible = "arm,mmu-500";
 829                         reg = <0x0 0xfd800000 0x0 0x20000>;
 830                         #iommu-cells = <1>;
 831                         #global-interrupts = <1>;
 832                         interrupt-parent = <&gic>;
 833                         interrupts = <0 155 4>,
 834                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 835                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 836                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 837                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 838                         mmu-masters = < &gem0 0x874
 839                                         &gem1 0x875
 840                                         &gem2 0x876
 841                                         &gem3 0x877
 842                                         &usb0 0x860
 843                                         &usb1 0x861
 844                                         &qspi 0x873
 845                                         &lpd_dma_chan1 0x868
 846                                         &lpd_dma_chan2 0x869
 847                                         &lpd_dma_chan3 0x86a
 848                                         &lpd_dma_chan4 0x86b
 849                                         &lpd_dma_chan5 0x86c
 850                                         &lpd_dma_chan6 0x86d
 851                                         &lpd_dma_chan7 0x86e
 852                                         &lpd_dma_chan8 0x86f
 853                                         &fpd_dma_chan1 0x14e8
 854                                         &fpd_dma_chan2 0x14e9
 855                                         &fpd_dma_chan3 0x14ea
 856                                         &fpd_dma_chan4 0x14eb
 857                                         &fpd_dma_chan5 0x14ec
 858                                         &fpd_dma_chan6 0x14ed
 859                                         &fpd_dma_chan7 0x14ee
 860                                         &fpd_dma_chan8 0x14ef
 861                                         &sdhci0 0x870
 862                                         &sdhci1 0x871
 863                                         &nand0 0x872>;
 864                 };
 865
 866                 spi0: spi@ff040000 {
 867                         compatible = "cdns,spi-r1p6";
 868                         status = "disabled";
 869                         interrupt-parent = <&gic>;
 870                         interrupts = <0 19 4>;
 871                         reg = <0x0 0xff040000 0x0 0x1000>;
 872                         clock-names = "ref_clk", "pclk";
 873                         #address-cells = <1>;
 874                         #size-cells = <0>;
 875                         power-domains = <&pd_spi0>;
 876                 };
 877
 878                 spi1: spi@ff050000 {
 879                         compatible = "cdns,spi-r1p6";
 880                         status = "disabled";
 881                         interrupt-parent = <&gic>;
 882                         interrupts = <0 20 4>;
 883                         reg = <0x0 0xff050000 0x0 0x1000>;
 884                         clock-names = "ref_clk", "pclk";
 885                         #address-cells = <1>;
 886                         #size-cells = <0>;
 887                         power-domains = <&pd_spi1>;
 888                 };
 889
 890                 ttc0: timer@ff110000 {
 891                         compatible = "cdns,ttc";
 892                         status = "disabled";
 893                         interrupt-parent = <&gic>;
 894                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 895                         reg = <0x0 0xff110000 0x0 0x1000>;
 896                         timer-width = <32>;
 897                         power-domains = <&pd_ttc0>;
 898                 };
 899
 900                 ttc1: timer@ff120000 {
 901                         compatible = "cdns,ttc";
 902                         status = "disabled";
 903                         interrupt-parent = <&gic>;
 904                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 905                         reg = <0x0 0xff120000 0x0 0x1000>;
 906                         timer-width = <32>;
 907                         power-domains = <&pd_ttc1>;
 908                 };
 909
 910                 ttc2: timer@ff130000 {
 911                         compatible = "cdns,ttc";
 912                         status = "disabled";
 913                         interrupt-parent = <&gic>;
 914                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 915                         reg = <0x0 0xff130000 0x0 0x1000>;
 916                         timer-width = <32>;
 917                         power-domains = <&pd_ttc2>;
 918                 };
 919
 920                 ttc3: timer@ff140000 {
 921                         compatible = "cdns,ttc";
 922                         status = "disabled";
 923                         interrupt-parent = <&gic>;
 924                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 925                         reg = <0x0 0xff140000 0x0 0x1000>;
 926                         timer-width = <32>;
 927                         power-domains = <&pd_ttc3>;
 928                 };
 929
 930                 uart0: serial@ff000000 {
 931                         u-boot,dm-pre-reloc;
 932                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 933                         status = "disabled";
 934                         interrupt-parent = <&gic>;
 935                         interrupts = <0 21 4>;
 936                         reg = <0x0 0xff000000 0x0 0x1000>;
 937                         clock-names = "uart_clk", "pclk";
 938                         power-domains = <&pd_uart0>;
 939                 };
 940
 941                 uart1: serial@ff010000 {
 942                         u-boot,dm-pre-reloc;
 943                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 944                         status = "disabled";
 945                         interrupt-parent = <&gic>;
 946                         interrupts = <0 22 4>;
 947                         reg = <0x0 0xff010000 0x0 0x1000>;
 948                         clock-names = "uart_clk", "pclk";
 949                         power-domains = <&pd_uart1>;
 950                 };
 951
 952                 usb0: usb0 {
 953                         #address-cells = <2>;
 954                         #size-cells = <2>;
 955                         status = "disabled";
 956                         compatible = "xlnx,zynqmp-dwc3";
 957                         clock-names = "bus_clk", "ref_clk";
 958                         clocks = <&clk125>, <&clk125>;
 959                         #stream-id-cells = <1>;
 960                         iommus = <&smmu 0x860>;
 961                         power-domains = <&pd_usb0>;
 962                         ranges;
 963
 964                         dwc3_0: dwc3@fe200000 {
 965                                 compatible = "snps,dwc3";
 966                                 status = "disabled";
 967                                 reg = <0x0 0xfe200000 0x0 0x40000>;
 968                                 interrupt-parent = <&gic>;
 969                                 interrupts = <0 65 4>;
 970                                 /* snps,quirk-frame-length-adjustment = <0x20>; */
 971                                 snps,refclk_fladj;
 972                         };
 973                 };
 974
 975                 usb1: usb1 {
 976                         #address-cells = <2>;
 977                         #size-cells = <2>;
 978                         status = "disabled";
 979                         compatible = "xlnx,zynqmp-dwc3";
 980                         clock-names = "bus_clk", "ref_clk";
 981                         clocks = <&clk125>, <&clk125>;
 982                         #stream-id-cells = <1>;
 983                         iommus = <&smmu 0x861>;
 984                         power-domains = <&pd_usb1>;
 985                         ranges;
 986
 987                         dwc3_1: dwc3@fe300000 {
 988                                 compatible = "snps,dwc3";
 989                                 status = "disabled";
 990                                 reg = <0x0 0xfe300000 0x0 0x40000>;
 991                                 interrupt-parent = <&gic>;
 992                                 interrupts = <0 70 4>;
 993                                 /* snps,quirk-frame-length-adjustment = <0x20>; */
 994                                 snps,refclk_fladj;
 995                         };
 996                 };
 997
 998                 watchdog0: watchdog@fd4d0000 {
 999                         compatible = "cdns,wdt-r1p2";
1000                         status = "disabled";
1001                         interrupt-parent = <&gic>;
1002                         interrupts = <0 113 1>;
1003                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
1004                         timeout-sec = <10>;
1005                 };
1006
1007                 xilinx_drm: xilinx_drm {
1008                         compatible = "xlnx,drm";
1009                         status = "disabled";
1010                         xlnx,encoder-slave = <&xlnx_dp>;
1011                         xlnx,connector-type = "DisplayPort";
1012                         xlnx,dp-sub = <&xlnx_dp_sub>;
1013                         planes {
1014                                 xlnx,pixel-format = "rgb565";
1015                                 plane0 {
1016                                         dmas = <&xlnx_dpdma 3>;
1017                                         dma-names = "dma0";
1018                                 };
1019                                 plane1 {
1020                                         dmas = <&xlnx_dpdma 0>,
1021                                                <&xlnx_dpdma 1>,
1022                                                <&xlnx_dpdma 2>;
1023                                         dma-names = "dma0", "dma1", "dma2";
1024                                 };
1025                         };
1026                 };
1027
1028                 xlnx_dp: dp@fd4a0000 {
1029                         compatible = "xlnx,v-dp";
1030                         status = "disabled";
1031                         reg = <0x0 0xfd4a0000 0x0 0x1000>;
1032                         interrupts = <0 119 4>;
1033                         interrupt-parent = <&gic>;
1034                         clock-names = "aclk", "aud_clk";
1035                         xlnx,dp-version = "v1.2";
1036                         xlnx,max-lanes = <2>;
1037                         xlnx,max-link-rate = <540000>;
1038                         xlnx,max-bpc = <16>;
1039                         xlnx,enable-ycrcb;
1040                         xlnx,colormetry = "rgb";
1041                         xlnx,bpc = <8>;
1042                         xlnx,audio-chan = <2>;
1043                         xlnx,dp-sub = <&xlnx_dp_sub>;
1044                         xlnx,max-pclock-frequency = <300000>;
1045                 };
1046
1047                 xlnx_dp_snd_card: dp_snd_card {
1048                         compatible = "xlnx,dp-snd-card";
1049                         status = "disabled";
1050                         xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
1051                         xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
1052                 };
1053
1054                 xlnx_dp_snd_codec0: dp_snd_codec0 {
1055                         compatible = "xlnx,dp-snd-codec";
1056                         status = "disabled";
1057                         clock-names = "aud_clk";
1058                 };
1059
1060                 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
1061                         compatible = "xlnx,dp-snd-pcm";
1062                         status = "disabled";
1063                         dmas = <&xlnx_dpdma 4>;
1064                         dma-names = "tx";
1065                 };
1066
1067                 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1068                         compatible = "xlnx,dp-snd-pcm";
1069                         status = "disabled";
1070                         dmas = <&xlnx_dpdma 5>;
1071                         dma-names = "tx";
1072                 };
1073
1074                 xlnx_dp_sub: dp_sub@fd4aa000 {
1075                         compatible = "xlnx,dp-sub";
1076                         status = "disabled";
1077                         reg = <0x0 0xfd4aa000 0x0 0x1000>,
1078                               <0x0 0xfd4ab000 0x0 0x1000>,
1079                               <0x0 0xfd4ac000 0x0 0x1000>;
1080                         reg-names = "blend", "av_buf", "aud";
1081                         xlnx,output-fmt = "rgb";
1082                         xlnx,vid-fmt = "yuyv";
1083                         xlnx,gfx-fmt = "rgb565";
1084                 };
1085
1086                 xlnx_dpdma: dma@fd4c0000 {
1087                         compatible = "xlnx,dpdma";
1088                         status = "disabled";
1089                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
1090                         interrupts = <0 122 4>;
1091                         interrupt-parent = <&gic>;
1092                         clock-names = "axi_clk";
1093                         dma-channels = <6>;
1094                         #dma-cells = <1>;
1095                         dma-video0channel {
1096                                 compatible = "xlnx,video0";
1097                         };
1098                         dma-video1channel {
1099                                 compatible = "xlnx,video1";
1100                         };
1101                         dma-video2channel {
1102                                 compatible = "xlnx,video2";
1103                         };
1104                         dma-graphicschannel {
1105                                 compatible = "xlnx,graphics";
1106                         };
1107                         dma-audio0channel {
1108                                 compatible = "xlnx,audio0";
1109                         };
1110                         dma-audio1channel {
1111                                 compatible = "xlnx,audio1";
1112                         };
1113                 };
1114         };
1115 };