arch/arm/dts/zynqmp-zcu111-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU111
   4  *
   5  * (C) Copyright 2017 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU111 RevA";
  20         compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &dcc;
  31                 spi0 = &qspi;
  32                 usb0 = &usb0;
  33         };
  34
  35         chosen {
  36                 bootargs = "earlycon";
  37                 stdout-path = "serial0:115200n8";
  38                 xlnx,eeprom = &eeprom;
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44                 /* Another 4GB connected to PL */
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 autorepeat;
  50                 sw19 {
  51                         label = "sw19";
  52                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  53                         linux,code = <KEY_DOWN>;
  54                         gpio-key,wakeup;
  55                         autorepeat;
  56                 };
  57         };
  58
  59         leds {
  60                 compatible = "gpio-leds";
  61                 heartbeat_led {
  62                         label = "heartbeat";
  63                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  64                         linux,default-trigger = "heartbeat";
  65                 };
  66         };
  67
  68         ina226-u67 {
  69                 compatible = "iio-hwmon";
  70                 io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
  71         };
  72         ina226-u59 {
  73                 compatible = "iio-hwmon";
  74                 io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
  75         };
  76         ina226-u61 {
  77                 compatible = "iio-hwmon";
  78                 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
  79         };
  80         ina226-u60 {
  81                 compatible = "iio-hwmon";
  82                 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
  83         };
  84         ina226-u64 {
  85                 compatible = "iio-hwmon";
  86                 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
  87         };
  88         ina226-u69 {
  89                 compatible = "iio-hwmon";
  90                 io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
  91         };
  92         ina226-u66 {
  93                 compatible = "iio-hwmon";
  94                 io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
  95         };
  96         ina226-u65 {
  97                 compatible = "iio-hwmon";
  98                 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
  99         };
 100         ina226-u63 {
 101                 compatible = "iio-hwmon";
 102                 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
 103         };
 104         ina226-u3 {
 105                 compatible = "iio-hwmon";
 106                 io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
 107         };
 108         ina226-u71 {
 109                 compatible = "iio-hwmon";
 110                 io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
 111         };
 112         ina226-u77 {
 113                 compatible = "iio-hwmon";
 114                 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
 115         };
 116         ina226-u73 {
 117                 compatible = "iio-hwmon";
 118                 io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
 119         };
 120         ina226-u79 {
 121                 compatible = "iio-hwmon";
 122                 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
 123         };
 124 };
 125
 126 &dcc {
 127         status = "okay";
 128 };
 129
 130 &fpd_dma_chan1 {
 131         status = "okay";
 132 };
 133
 134 &fpd_dma_chan2 {
 135         status = "okay";
 136 };
 137
 138 &fpd_dma_chan3 {
 139         status = "okay";
 140 };
 141
 142 &fpd_dma_chan4 {
 143         status = "okay";
 144 };
 145
 146 &fpd_dma_chan5 {
 147         status = "okay";
 148 };
 149
 150 &fpd_dma_chan6 {
 151         status = "okay";
 152 };
 153
 154 &fpd_dma_chan7 {
 155         status = "okay";
 156 };
 157
 158 &fpd_dma_chan8 {
 159         status = "okay";
 160 };
 161
 162 &gem3 {
 163         status = "okay";
 164         phy-handle = <&phy0>;
 165         phy-mode = "rgmii-id";
 166         phy0: ethernet-phy@c {
 167                 reg = <0xc>;
 168                 ti,rx-internal-delay = <0x8>;
 169                 ti,tx-internal-delay = <0xa>;
 170                 ti,fifo-depth = <0x1>;
 171         };
 172 };
 173
 174 &gpio {
 175         status = "okay";
 176 };
 177
 178 &gpu {
 179         status = "okay";
 180 };
 181
 182 &i2c0 {
 183         status = "okay";
 184         clock-frequency = <400000>;
 185
 186         tca6416_u22: gpio@20 {
 187                 compatible = "ti,tca6416";
 188                 reg = <0x20>;
 189                 gpio-controller; /* interrupt not connected */
 190                 #gpio-cells = <2>;
 191                 /*
 192                  * IRQ not connected
 193                  * Lines:
 194                  * 0 - MAX6643_OT_B
 195                  * 1 - MAX6643_FANFAIL_B
 196                  * 2 - MIO26_PMU_INPUT_LS
 197                  * 4 - SFP_SI5382_INT_ALM
 198                  * 5 - IIC_MUX_RESET_B
 199                  * 6 - GEM3_EXP_RESET_B
 200                  * 10 - FMCP_HSPC_PRSNT_M2C_B
 201                  * 11 - CLK_SPI_MUX_SEL0
 202                  * 12 - CLK_SPI_MUX_SEL1
 203                  * 16 - IRPS5401_ALERT_B
 204                  * 17 - INA226_PMBUS_ALERT
 205                  * 3, 7, 13-15 - not connected
 206                  */
 207         };
 208
 209         i2c-mux@75 { /* u23 */
 210                 compatible = "nxp,pca9544";
 211                 #address-cells = <1>;
 212                 #size-cells = <0>;
 213                 reg = <0x75>;
 214                 i2c@0 {
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217                         reg = <0>;
 218                         /* PS_PMBUS */
 219                         /* PMBUS_ALERT done via pca9544 */
 220                         u67: ina226@40 { /* u67 */
 221                                 compatible = "ti,ina226";
 222                                 #io-channel-cells = <1>;
 223                                 reg = <0x40>;
 224                                 shunt-resistor = <2000>;
 225                         };
 226                         u59: ina226@41 { /* u59 */
 227                                 compatible = "ti,ina226";
 228                                 #io-channel-cells = <1>;
 229                                 reg = <0x41>;
 230                                 shunt-resistor = <5000>;
 231                         };
 232                         u61: ina226@42 { /* u61 */
 233                                 compatible = "ti,ina226";
 234                                 #io-channel-cells = <1>;
 235                                 reg = <0x42>;
 236                                 shunt-resistor = <5000>;
 237                         };
 238                         u60: ina226@43 { /* u60 */
 239                                 compatible = "ti,ina226";
 240                                 #io-channel-cells = <1>;
 241                                 reg = <0x43>;
 242                                 shunt-resistor = <5000>;
 243                         };
 244                         u64: ina226@45 { /* u64 */
 245                                 compatible = "ti,ina226";
 246                                 #io-channel-cells = <1>;
 247                                 reg = <0x45>;
 248                                 shunt-resistor = <5000>;
 249                         };
 250                         u69: ina226@46 { /* u69 */
 251                                 compatible = "ti,ina226";
 252                                 #io-channel-cells = <1>;
 253                                 reg = <0x46>;
 254                                 shunt-resistor = <2000>;
 255                         };
 256                         u66: ina226@47 { /* u66 */
 257                                 compatible = "ti,ina226";
 258                                 #io-channel-cells = <1>;
 259                                 reg = <0x47>;
 260                                 shunt-resistor = <5000>;
 261                         };
 262                         u65: ina226@48 { /* u65 */
 263                                 compatible = "ti,ina226";
 264                                 #io-channel-cells = <1>;
 265                                 reg = <0x48>;
 266                                 shunt-resistor = <5000>;
 267                         };
 268                         u63: ina226@49 { /* u63 */
 269                                 compatible = "ti,ina226";
 270                                 #io-channel-cells = <1>;
 271                                 reg = <0x49>;
 272                                 shunt-resistor = <5000>;
 273                         };
 274                         u3: ina226@4a { /* u3 */
 275                                 compatible = "ti,ina226";
 276                                 #io-channel-cells = <1>;
 277                                 reg = <0x4a>;
 278                                 shunt-resistor = <5000>;
 279                         };
 280                         u71: ina226@4b { /* u71 */
 281                                 compatible = "ti,ina226";
 282                                 #io-channel-cells = <1>;
 283                                 reg = <0x4b>;
 284                                 shunt-resistor = <5000>;
 285                         };
 286                         u77: ina226@4c { /* u77 */
 287                                 compatible = "ti,ina226";
 288                                 #io-channel-cells = <1>;
 289                                 reg = <0x4c>;
 290                                 shunt-resistor = <5000>;
 291                         };
 292                         u73: ina226@4d { /* u73 */
 293                                 compatible = "ti,ina226";
 294                                 #io-channel-cells = <1>;
 295                                 reg = <0x4d>;
 296                                 shunt-resistor = <5000>;
 297                         };
 298                         u79: ina226@4e { /* u79 */
 299                                 compatible = "ti,ina226";
 300                                 #io-channel-cells = <1>;
 301                                 reg = <0x4e>;
 302                                 shunt-resistor = <5000>;
 303                         };
 304                 };
 305                 i2c@1 {
 306                         #address-cells = <1>;
 307                         #size-cells = <0>;
 308                         reg = <1>;
 309                         /* NC */
 310                 };
 311                 i2c@2 {
 312                         #address-cells = <1>;
 313                         #size-cells = <0>;
 314                         reg = <2>;
 315                         irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
 316                                 #clock-cells = <0>;
 317                                 compatible = "infineon,irps5401";
 318                                 reg = <0x43>;
 319                         };
 320                         irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
 321                                 #clock-cells = <0>;
 322                                 compatible = "infineon,irps5401";
 323                                 reg = <0x44>;
 324                         };
 325                         irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
 326                                 #clock-cells = <0>;
 327                                 compatible = "infineon,irps5401";
 328                                 reg = <0x45>;
 329                         };
 330                         /* u68 IR38064 +0 */
 331                         /* u70 IR38060 +1 */
 332                         /* u74 IR38060 +2 */
 333                         /* u75 IR38060 +6 */
 334                         /* J19 header too */
 335
 336                 };
 337                 i2c@3 {
 338                         #address-cells = <1>;
 339                         #size-cells = <0>;
 340                         reg = <3>;
 341                         /* SYSMON */
 342                 };
 343         };
 344 };
 345
 346 &i2c1 {
 347         status = "okay";
 348         clock-frequency = <400000>;
 349
 350         i2c-mux@74 { /* u26 */
 351                 compatible = "nxp,pca9548";
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 reg = <0x74>;
 355                 i2c@0 {
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         reg = <0>;
 359                         /*
 360                          * IIC_EEPROM 1kB memory which uses 256B blocks
 361                          * where every block has different address.
 362                          *    0 - 256B address 0x54
 363                          * 256B - 512B address 0x55
 364                          * 512B - 768B address 0x56
 365                          * 768B - 1024B address 0x57
 366                          */
 367                         eeprom: eeprom@54 { /* u88 */
 368                                 compatible = "atmel,24c08";
 369                                 reg = <0x54>;
 370                         };
 371                 };
 372                 i2c@1 {
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         reg = <1>;
 376                         si5341: clock-generator@36 { /* SI5341 - u46 */
 377                                 compatible = "si5341";
 378                                 reg = <0x36>;
 379                         };
 380
 381                 };
 382                 i2c@2 {
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         reg = <2>;
 386                         si570_1: clock-generator@5d { /* USER SI570 - u47 */
 387                                 #clock-cells = <0>;
 388                                 compatible = "silabs,si570";
 389                                 reg = <0x5d>;
 390                                 temperature-stability = <50>;
 391                                 factory-fout = <300000000>;
 392                                 clock-frequency = <300000000>;
 393                                 clock-output-names = "si570_user";
 394                         };
 395                 };
 396                 i2c@3 {
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         reg = <3>;
 400                         si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
 401                                 #clock-cells = <0>;
 402                                 compatible = "silabs,si570";
 403                                 reg = <0x5d>;
 404                                 temperature-stability = <50>;
 405                                 factory-fout = <156250000>;
 406                                 clock-frequency = <148500000>;
 407                                 clock-output-names = "si570_mgt";
 408                         };
 409                 };
 410                 i2c@4 {
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         reg = <4>;
 414                         si5328: clock-generator@69 { /* SI5328 - u48 */
 415                                 compatible = "silabs,si5328";
 416                                 reg = <0x69>;
 417                         };
 418                 };
 419                 i2c@5 {
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         reg = <5>;
 423                                 sc18is603@2f { /* sc18is602 - u93 */
 424                                         compatible = "nxp,sc18is603";
 425                                         reg = <0x2f>;
 426                                         /* 4 gpios for CS not handled by driver */
 427                                         /*
 428                                          * USB2ANY cable or
 429                                          * LMK04208 - u90 or
 430                                          * LMX2594 - u102 or
 431                                          * LMX2594 - u103 or
 432                                          * LMX2594 - u104
 433                                          */
 434                                 };
 435                 };
 436                 i2c@6 {
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         reg = <6>;
 440                         /* FMC connector */
 441                 };
 442                 /* 7 NC */
 443         };
 444
 445         i2c-mux@75 {
 446                 compatible = "nxp,pca9548"; /* u27 */
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 reg = <0x75>;
 450
 451                 i2c@0 {
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         reg = <0>;
 455                         /* FMCP_HSPC_IIC */
 456                 };
 457                 i2c@1 {
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         reg = <1>;
 461                         /* NC */
 462                 };
 463                 i2c@2 {
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                         reg = <2>;
 467                         /* SYSMON */
 468                 };
 469                 i2c@3 {
 470                         #address-cells = <1>;
 471                         #size-cells = <0>;
 472                         reg = <3>;
 473                         /* DDR4 SODIMM */
 474                 };
 475                 i2c@4 {
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         reg = <4>;
 479                         /* SFP3 */
 480                 };
 481                 i2c@5 {
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                         reg = <5>;
 485                         /* SFP2 */
 486                 };
 487                 i2c@6 {
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                         reg = <6>;
 491                         /* SFP1 */
 492                 };
 493                 i2c@7 {
 494                         #address-cells = <1>;
 495                         #size-cells = <0>;
 496                         reg = <7>;
 497                         /* SFP0 */
 498                 };
 499         };
 500 };
 501
 502 &qspi {
 503         status = "okay";
 504         is-dual = <1>;
 505         flash@0 {
 506                 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
 507                 #address-cells = <1>;
 508                 #size-cells = <1>;
 509                 reg = <0x0>;
 510                 spi-tx-bus-width = <1>;
 511                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 512                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 513                 partition@qspi-fsbl-uboot { /* for testing purpose */
 514                         label = "qspi-fsbl-uboot";
 515                         reg = <0x0 0x100000>;
 516                 };
 517                 partition@qspi-linux { /* for testing purpose */
 518                         label = "qspi-linux";
 519                         reg = <0x100000 0x500000>;
 520                 };
 521                 partition@qspi-device-tree { /* for testing purpose */
 522                         label = "qspi-device-tree";
 523                         reg = <0x600000 0x20000>;
 524                 };
 525                 partition@qspi-rootfs { /* for testing purpose */
 526                         label = "qspi-rootfs";
 527                         reg = <0x620000 0x5E0000>;
 528                 };
 529         };
 530 };
 531
 532 &rtc {
 533         status = "okay";
 534 };
 535
 536 &sata {
 537         status = "okay";
 538         /* SATA OOB timing settings */
 539         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 540         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 541         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 542         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 543         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 544         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 545         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 546         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 547         phy-names = "sata-phy";
 548         phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
 549 };
 550
 551 /* SD1 with level shifter */
 552 &sdhci1 {
 553         status = "okay";
 554         no-1-8-v;
 555         disable-wp;
 556         xlnx,mio_bank = <1>;
 557 };
 558
 559 &serdes {
 560         status = "okay";
 561 };
 562
 563 &uart0 {
 564         status = "okay";
 565 };
 566
 567 /* ULPI SMSC USB3320 */
 568 &usb0 {
 569         status = "okay";
 570 };
 571
 572 &dwc3_0 {
 573         status = "okay";
 574         dr_mode = "host";
 575         snps,usb3_lpm_capable;
 576         phy-names = "usb3-phy";
 577         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 578 };