arch/arm/dts/zynqmp-zcu111-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU111
   4  *
   5  * (C) Copyright 2017 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU111 RevA";
  20         compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &dcc;
  31                 spi0 = &qspi;
  32                 usb0 = &usb0;
  33         };
  34
  35         chosen {
  36                 bootargs = "earlycon";
  37                 stdout-path = "serial0:115200n8";
  38         };
  39
  40         memory@0 {
  41                 device_type = "memory";
  42                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  43                 /* Another 4GB connected to PL */
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 autorepeat;
  51                 sw19 {
  52                         label = "sw19";
  53                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  54                         linux,code = <KEY_DOWN>;
  55                         gpio-key,wakeup;
  56                         autorepeat;
  57                 };
  58         };
  59
  60         leds {
  61                 compatible = "gpio-leds";
  62                 heartbeat_led {
  63                         label = "heartbeat";
  64                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  65                         linux,default-trigger = "heartbeat";
  66                 };
  67         };
  68 };
  69
  70 &dcc {
  71         status = "okay";
  72 };
  73
  74 &fpd_dma_chan1 {
  75         status = "okay";
  76 };
  77
  78 &fpd_dma_chan2 {
  79         status = "okay";
  80 };
  81
  82 &fpd_dma_chan3 {
  83         status = "okay";
  84 };
  85
  86 &fpd_dma_chan4 {
  87         status = "okay";
  88 };
  89
  90 &fpd_dma_chan5 {
  91         status = "okay";
  92 };
  93
  94 &fpd_dma_chan6 {
  95         status = "okay";
  96 };
  97
  98 &fpd_dma_chan7 {
  99         status = "okay";
 100 };
 101
 102 &fpd_dma_chan8 {
 103         status = "okay";
 104 };
 105
 106 &gem3 {
 107         status = "okay";
 108         phy-handle = <&phy0>;
 109         phy-mode = "rgmii-id";
 110         phy0: phy@c {
 111                 reg = <0xc>;
 112                 ti,rx-internal-delay = <0x8>;
 113                 ti,tx-internal-delay = <0xa>;
 114                 ti,fifo-depth = <0x1>;
 115         };
 116 };
 117
 118 &gpio {
 119         status = "okay";
 120 };
 121
 122 &gpu {
 123         status = "okay";
 124 };
 125
 126 &i2c0 {
 127         status = "okay";
 128         clock-frequency = <400000>;
 129
 130         tca6416_u22: gpio@20 {
 131                 compatible = "ti,tca6416";
 132                 reg = <0x20>;
 133                 gpio-controller; /* interrupt not connected */
 134                 #gpio-cells = <2>;
 135                 /*
 136                  * IRQ not connected
 137                  * Lines:
 138                  * 0 - MAX6643_OT_B
 139                  * 1 - MAX6643_FANFAIL_B
 140                  * 2 - MIO26_PMU_INPUT_LS
 141                  * 4 - SFP_SI5382_INT_ALM
 142                  * 5 - IIC_MUX_RESET_B
 143                  * 6 - GEM3_EXP_RESET_B
 144                  * 10 - FMCP_HSPC_PRSNT_M2C_B
 145                  * 11 - CLK_SPI_MUX_SEL0
 146                  * 12 - CLK_SPI_MUX_SEL1
 147                  * 16 - IRPS5401_ALERT_B
 148                  * 17 - INA226_PMBUS_ALERT
 149                  * 3, 7, 13-15 - not connected
 150                  */
 151         };
 152
 153         i2c-mux@75 { /* u23 */
 154                 compatible = "nxp,pca9544";
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157                 reg = <0x75>;
 158                 i2c@0 {
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                         reg = <0>;
 162                         /* PS_PMBUS */
 163                         /* PMBUS_ALERT done via pca9544 */
 164                         ina226@40 { /* u67 */
 165                                 compatible = "ti,ina226";
 166                                 reg = <0x40>;
 167                                 shunt-resistor = <2000>;
 168                         };
 169                         ina226@41 { /* u59 */
 170                                 compatible = "ti,ina226";
 171                                 reg = <0x41>;
 172                                 shunt-resistor = <5000>;
 173                         };
 174                         ina226@42 { /* u61 */
 175                                 compatible = "ti,ina226";
 176                                 reg = <0x42>;
 177                                 shunt-resistor = <5000>;
 178                         };
 179                         ina226@43 { /* u60 */
 180                                 compatible = "ti,ina226";
 181                                 reg = <0x43>;
 182                                 shunt-resistor = <5000>;
 183                         };
 184                         ina226@45 { /* u64 */
 185                                 compatible = "ti,ina226";
 186                                 reg = <0x45>;
 187                                 shunt-resistor = <5000>;
 188                         };
 189                         ina226@46 { /* u69 */
 190                                 compatible = "ti,ina226";
 191                                 reg = <0x46>;
 192                                 shunt-resistor = <2000>;
 193                         };
 194                         ina226@47 { /* u66 */
 195                                 compatible = "ti,ina226";
 196                                 reg = <0x47>;
 197                                 shunt-resistor = <5000>;
 198                         };
 199                         ina226@48 { /* u65 */
 200                                 compatible = "ti,ina226";
 201                                 reg = <0x48>;
 202                                 shunt-resistor = <5000>;
 203                         };
 204                         ina226@49 { /* u63 */
 205                                 compatible = "ti,ina226";
 206                                 reg = <0x49>;
 207                                 shunt-resistor = <5000>;
 208                         };
 209                         ina226@4a { /* u3 */
 210                                 compatible = "ti,ina226";
 211                                 reg = <0x4a>;
 212                                 shunt-resistor = <5000>;
 213                         };
 214                         ina226@4b { /* u71 */
 215                                 compatible = "ti,ina226";
 216                                 reg = <0x4b>;
 217                                 shunt-resistor = <5000>;
 218                         };
 219                         ina226@4c { /* u77 */
 220                                 compatible = "ti,ina226";
 221                                 reg = <0x4c>;
 222                                 shunt-resistor = <5000>;
 223                         };
 224                         ina226@4d { /* u73 */
 225                                 compatible = "ti,ina226";
 226                                 reg = <0x4d>;
 227                                 shunt-resistor = <5000>;
 228                         };
 229                         ina226@4e { /* u79 */
 230                                 compatible = "ti,ina226";
 231                                 reg = <0x4e>;
 232                                 shunt-resistor = <5000>;
 233                         };
 234                 };
 235                 i2c@1 {
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                         reg = <1>;
 239                         /* NC */
 240                 };
 241                 i2c@2 {
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244                         reg = <2>;
 245                         irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
 246                                 #clock-cells = <0>;
 247                                 compatible = "infineon,irps5401";
 248                                 reg = <0x43>;
 249                         };
 250                         irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
 251                                 #clock-cells = <0>;
 252                                 compatible = "infineon,irps5401";
 253                                 reg = <0x44>;
 254                         };
 255                         irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
 256                                 #clock-cells = <0>;
 257                                 compatible = "infineon,irps5401";
 258                                 reg = <0x45>;
 259                         };
 260                         /* u68 IR38064 +0 */
 261                         /* u70 IR38060 +1 */
 262                         /* u74 IR38060 +2 */
 263                         /* u75 IR38060 +6 */
 264                         /* J19 header too */
 265
 266                 };
 267                 i2c@3 {
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                         reg = <3>;
 271                         /* SYSMON */
 272                 };
 273         };
 274 };
 275
 276 &i2c1 {
 277         status = "okay";
 278         clock-frequency = <400000>;
 279
 280         i2c-mux@74 { /* u26 */
 281                 compatible = "nxp,pca9548";
 282                 #address-cells = <1>;
 283                 #size-cells = <0>;
 284                 reg = <0x74>;
 285                 i2c@0 {
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288                         reg = <0>;
 289                         /*
 290                          * IIC_EEPROM 1kB memory which uses 256B blocks
 291                          * where every block has different address.
 292                          *    0 - 256B address 0x54
 293                          * 256B - 512B address 0x55
 294                          * 512B - 768B address 0x56
 295                          * 768B - 1024B address 0x57
 296                          */
 297                         eeprom: eeprom@54 { /* u88 */
 298                                 compatible = "atmel,24c08";
 299                                 reg = <0x54>;
 300                         };
 301                 };
 302                 i2c@1 {
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         reg = <1>;
 306                         si5341: clock-generator@36 { /* SI5341 - u46 */
 307                                 compatible = "si5341";
 308                                 reg = <0x36>;
 309                         };
 310
 311                 };
 312                 i2c@2 {
 313                         #address-cells = <1>;
 314                         #size-cells = <0>;
 315                         reg = <2>;
 316                         si570_1: clock-generator@5d { /* USER SI570 - u47 */
 317                                 #clock-cells = <0>;
 318                                 compatible = "silabs,si570";
 319                                 reg = <0x5d>;
 320                                 temperature-stability = <50>;
 321                                 factory-fout = <300000000>;
 322                                 clock-frequency = <300000000>;
 323                         };
 324                 };
 325                 i2c@3 {
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                         reg = <3>;
 329                         si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
 330                                 #clock-cells = <0>;
 331                                 compatible = "silabs,si570";
 332                                 reg = <0x5d>;
 333                                 temperature-stability = <50>;
 334                                 factory-fout = <156250000>;
 335                                 clock-frequency = <148500000>;
 336                         };
 337                 };
 338                 i2c@4 {
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         reg = <4>;
 342                         si5328: clock-generator@69 { /* SI5328 - u48 */
 343                                 compatible = "silabs,si5328";
 344                                 reg = <0x69>;
 345                         };
 346                 };
 347                 i2c@5 {
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                         reg = <5>;
 351                                 sc18is603@2f { /* sc18is602 - u93 */
 352                                         compatible = "nxp,sc18is603";
 353                                         reg = <0x2f>;
 354                                         /* 4 gpios for CS not handled by driver */
 355                                         /*
 356                                          * USB2ANY cable or
 357                                          * LMK04208 - u90 or
 358                                          * LMX2594 - u102 or
 359                                          * LMX2594 - u103 or
 360                                          * LMX2594 - u104
 361                                          */
 362                                 };
 363                 };
 364                 i2c@6 {
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         reg = <6>;
 368                         /* FMC connector */
 369                 };
 370                 /* 7 NC */
 371         };
 372
 373         i2c-mux@75 {
 374                 compatible = "nxp,pca9548"; /* u27 */
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 reg = <0x75>;
 378
 379                 i2c@0 {
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         reg = <0>;
 383                         /* FMCP_HSPC_IIC */
 384                 };
 385                 i2c@1 {
 386                         #address-cells = <1>;
 387                         #size-cells = <0>;
 388                         reg = <1>;
 389                         /* NC */
 390                 };
 391                 i2c@2 {
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                         reg = <2>;
 395                         /* SYSMON */
 396                 };
 397                 i2c@3 {
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         reg = <3>;
 401                         /* DDR4 SODIMM */
 402                         dev@19 { /* u-boot detection FIXME */
 403                                 compatible = "xxx";
 404                                 reg = <0x19>;
 405                         };
 406                         dev@30 { /* u-boot detection */
 407                                 compatible = "xxx";
 408                                 reg = <0x30>;
 409                         };
 410                         dev@35 { /* u-boot detection */
 411                                 compatible = "xxx";
 412                                 reg = <0x35>;
 413                         };
 414                         dev@36 { /* u-boot detection */
 415                                 compatible = "xxx";
 416                                 reg = <0x36>;
 417                         };
 418                         dev@51 { /* u-boot detection - maybe SPD */
 419                                 compatible = "xxx";
 420                                 reg = <0x51>;
 421                         };
 422                 };
 423                 i2c@4 {
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426                         reg = <4>;
 427                         /* SFP3 */
 428                 };
 429                 i2c@5 {
 430                         #address-cells = <1>;
 431                         #size-cells = <0>;
 432                         reg = <5>;
 433                         /* SFP2 */
 434                 };
 435                 i2c@6 {
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         reg = <6>;
 439                         /* SFP1 */
 440                 };
 441                 i2c@7 {
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                         reg = <7>;
 445                         /* SFP0 */
 446                 };
 447         };
 448 };
 449
 450 &qspi {
 451         status = "okay";
 452         is-dual = <1>;
 453         flash@0 {
 454                 compatible = "m25p80"; /* 32MB */
 455                 #address-cells = <1>;
 456                 #size-cells = <1>;
 457                 reg = <0x0>;
 458                 spi-tx-bus-width = <1>;
 459                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 460                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 461                 partition@qspi-fsbl-uboot { /* for testing purpose */
 462                         label = "qspi-fsbl-uboot";
 463                         reg = <0x0 0x100000>;
 464                 };
 465                 partition@qspi-linux { /* for testing purpose */
 466                         label = "qspi-linux";
 467                         reg = <0x100000 0x500000>;
 468                 };
 469                 partition@qspi-device-tree { /* for testing purpose */
 470                         label = "qspi-device-tree";
 471                         reg = <0x600000 0x20000>;
 472                 };
 473                 partition@qspi-rootfs { /* for testing purpose */
 474                         label = "qspi-rootfs";
 475                         reg = <0x620000 0x5E0000>;
 476                 };
 477         };
 478 };
 479
 480 &rtc {
 481         status = "okay";
 482 };
 483
 484 &sata {
 485         status = "okay";
 486         /* SATA OOB timing settings */
 487         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 488         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 489         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 490         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 491         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 492         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 493         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 494         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 495         phy-names = "sata-phy";
 496         phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
 497 };
 498
 499 /* SD1 with level shifter */
 500 &sdhci1 {
 501         status = "okay";
 502         no-1-8-v;
 503         xlnx,mio_bank = <1>;
 504 };
 505
 506 &serdes {
 507         status = "okay";
 508 };
 509
 510 &uart0 {
 511         status = "okay";
 512 };
 513
 514 /* ULPI SMSC USB3320 */
 515 &usb0 {
 516         status = "okay";
 517 };
 518
 519 &dwc3_0 {
 520         status = "okay";
 521         dr_mode = "host";
 522         snps,usb3_lpm_capable;
 523         phy-names = "usb3-phy";
 524         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 525 };