1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/phy/phy.h>
18 model = "ZynqMP ZCU104 RevC";
19 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
35 bootargs = "earlycon";
36 stdout-path = "serial0:115200n8";
37 xlnx,eeprom = &eeprom;
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>;
57 phy-mode = "rgmii-id";
60 ti,rx-internal-delay = <0x8>;
61 ti,tx-internal-delay = <0xa>;
62 ti,fifo-depth = <0x1>;
76 clock-frequency = <400000>;
78 tca6416_u97: gpio@20 {
79 compatible = "ti,tca6416";
86 * 0 - IRPS5401_ALERT_B
87 * 1 - HDMI_8T49N241_INT_ALM
89 * 3 - MAX6643_FANFAIL_B
91 * 6 - GEM3_EXP_RESET_B
92 * 7 - FMC_LPC_PRSNT_M2C_B
93 * 4, 10 - 17 - not connected
97 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
98 i2c-mux@74 { /* u34 */
99 compatible = "nxp,pca9548";
100 #address-cells = <1>;
104 #address-cells = <1>;
108 * IIC_EEPROM 1kB memory which uses 256B blocks
109 * where every block has different address.
110 * 0 - 256B address 0x54
111 * 256B - 512B address 0x55
112 * 512B - 768B address 0x56
113 * 768B - 1024B address 0x57
115 eeprom: eeprom@54 { /* u23 */
116 compatible = "atmel,24c08";
118 #address-cells = <1>;
124 #address-cells = <1>;
127 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
128 compatible = "idt,8t49n287";
134 #address-cells = <1>;
137 irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
139 compatible = "infineon,irps5401";
142 irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
144 compatible = "infineon,irps5401";
150 #address-cells = <1>;
153 ina226@40 { /* u183 */
154 compatible = "ti,ina226";
156 shunt-resistor = <5000>;
161 #address-cells = <1>;
167 #address-cells = <1>;
172 /* 4, 6 not connected */
179 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
180 #address-cells = <1>;
183 spi-tx-bus-width = <1>;
184 spi-rx-bus-width = <4>;
185 spi-max-frequency = <108000000>; /* Based on DC1 spec */
186 partition@qspi-fsbl-uboot { /* for testing purpose */
187 label = "qspi-fsbl-uboot";
188 reg = <0x0 0x100000>;
190 partition@qspi-linux { /* for testing purpose */
191 label = "qspi-linux";
192 reg = <0x100000 0x500000>;
194 partition@qspi-device-tree { /* for testing purpose */
195 label = "qspi-device-tree";
196 reg = <0x600000 0x20000>;
198 partition@qspi-rootfs { /* for testing purpose */
199 label = "qspi-rootfs";
200 reg = <0x620000 0x5E0000>;
211 /* SATA OOB timing settings */
212 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
213 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
214 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
215 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
216 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
217 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
218 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
219 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
220 phy-names = "sata-phy";
221 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
224 /* SD1 with level shifter */
244 /* ULPI SMSC USB3320 */
252 snps,usb3_lpm_capable;
253 phy-names = "usb3-phy";
254 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
255 maximum-speed = "super-speed";