arch/arm/dts/zynqmp-zcu104-revC.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU104
   4  *
   5  * (C) Copyright 2017 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/phy/phy.h>
  16
  17 / {
  18         model = "ZynqMP ZCU104 RevC";
  19         compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
  20
  21         aliases {
  22                 ethernet0 = &gem3;
  23                 gpio0 = &gpio;
  24                 i2c0 = &i2c1;
  25                 mmc0 = &sdhci1;
  26                 rtc0 = &rtc;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &dcc;
  30                 spi0 = &qspi;
  31                 usb0 = &usb0;
  32         };
  33
  34         chosen {
  35                 bootargs = "earlycon";
  36                 stdout-path = "serial0:115200n8";
  37                 xlnx,eeprom = &eeprom;
  38         };
  39
  40         memory@0 {
  41                 device_type = "memory";
  42                 reg = <0x0 0x0 0x0 0x80000000>;
  43         };
  44
  45         ina226 {
  46                 compatible = "iio-hwmon";
  47                 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
  48         };
  49 };
  50
  51 &can1 {
  52         status = "okay";
  53 };
  54
  55 &dcc {
  56         status = "okay";
  57 };
  58
  59 &fpd_dma_chan1 {
  60         status = "okay";
  61 };
  62
  63 &fpd_dma_chan2 {
  64         status = "okay";
  65 };
  66
  67 &fpd_dma_chan3 {
  68         status = "okay";
  69 };
  70
  71 &fpd_dma_chan4 {
  72         status = "okay";
  73 };
  74
  75 &fpd_dma_chan5 {
  76         status = "okay";
  77 };
  78
  79 &fpd_dma_chan6 {
  80         status = "okay";
  81 };
  82
  83 &fpd_dma_chan7 {
  84         status = "okay";
  85 };
  86
  87 &fpd_dma_chan8 {
  88         status = "okay";
  89 };
  90
  91 &gem3 {
  92         status = "okay";
  93         phy-handle = <&phy0>;
  94         phy-mode = "rgmii-id";
  95         phy0: ethernet-phy@c {
  96                 reg = <0xc>;
  97                 ti,rx-internal-delay = <0x8>;
  98                 ti,tx-internal-delay = <0xa>;
  99                 ti,fifo-depth = <0x1>;
 100         };
 101 };
 102
 103 &gpio {
 104         status = "okay";
 105 };
 106
 107 &gpu {
 108         status = "okay";
 109 };
 110
 111 &i2c1 {
 112         status = "okay";
 113         clock-frequency = <400000>;
 114
 115         tca6416_u97: gpio@20 {
 116                 compatible = "ti,tca6416";
 117                 reg = <0x20>;
 118                 gpio-controller;
 119                 #gpio-cells = <2>;
 120                 /*
 121                  * IRQ not connected
 122                  * Lines:
 123                  * 0 - IRPS5401_ALERT_B
 124                  * 1 - HDMI_8T49N241_INT_ALM
 125                  * 2 - MAX6643_OT_B
 126                  * 3 - MAX6643_FANFAIL_B
 127                  * 5 - IIC_MUX_RESET_B
 128                  * 6 - GEM3_EXP_RESET_B
 129                  * 7 - FMC_LPC_PRSNT_M2C_B
 130                  * 4, 10 - 17 - not connected
 131                  */
 132         };
 133
 134         /* Another connection to this bus via PL i2c via PCA9306 - u45 */
 135         i2c-mux@74 { /* u34 */
 136                 compatible = "nxp,pca9548";
 137                 #address-cells = <1>;
 138                 #size-cells = <0>;
 139                 reg = <0x74>;
 140                 i2c@0 {
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         reg = <0>;
 144                         /*
 145                          * IIC_EEPROM 1kB memory which uses 256B blocks
 146                          * where every block has different address.
 147                          *    0 - 256B address 0x54
 148                          * 256B - 512B address 0x55
 149                          * 512B - 768B address 0x56
 150                          * 768B - 1024B address 0x57
 151                          */
 152                         eeprom: eeprom@54 { /* u23 */
 153                                 compatible = "atmel,24c08";
 154                                 reg = <0x54>;
 155                                 #address-cells = <1>;
 156                                 #size-cells = <1>;
 157                         };
 158                 };
 159
 160                 i2c@1 {
 161                         #address-cells = <1>;
 162                         #size-cells = <0>;
 163                         reg = <1>;
 164                         clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
 165                                 compatible = "idt,8t49n287";
 166                                 reg = <0x6c>;
 167                         };
 168                 };
 169
 170                 i2c@2 {
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         reg = <2>;
 174                         irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
 175                                 #clock-cells = <0>;
 176                                 compatible = "infineon,irps5401";
 177                                 reg = <0x43>;
 178                         };
 179                         irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
 180                                 #clock-cells = <0>;
 181                                 compatible = "infineon,irps5401";
 182                                 reg = <0x4d>;
 183                         };
 184                 };
 185
 186                 i2c@3 {
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         reg = <3>;
 190                         u183: ina226@40 { /* u183 */
 191                                 compatible = "ti,ina226";
 192                                 #io-channel-cells = <1>;
 193                                 reg = <0x40>;
 194                                 shunt-resistor = <5000>;
 195                         };
 196                 };
 197
 198                 i2c@5 {
 199                         #address-cells = <1>;
 200                         #size-cells = <0>;
 201                         reg = <5>;
 202                 };
 203
 204                 i2c@7 {
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         reg = <7>;
 208                 };
 209
 210                 /* 4, 6 not connected */
 211         };
 212 };
 213
 214 &qspi {
 215         status = "okay";
 216         flash@0 {
 217                 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
 218                 #address-cells = <1>;
 219                 #size-cells = <1>;
 220                 reg = <0x0>;
 221                 spi-tx-bus-width = <1>;
 222                 spi-rx-bus-width = <4>;
 223                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 224                 partition@qspi-fsbl-uboot { /* for testing purpose */
 225                         label = "qspi-fsbl-uboot";
 226                         reg = <0x0 0x100000>;
 227                 };
 228                 partition@qspi-linux { /* for testing purpose */
 229                         label = "qspi-linux";
 230                         reg = <0x100000 0x500000>;
 231                 };
 232                 partition@qspi-device-tree { /* for testing purpose */
 233                         label = "qspi-device-tree";
 234                         reg = <0x600000 0x20000>;
 235                 };
 236                 partition@qspi-rootfs { /* for testing purpose */
 237                         label = "qspi-rootfs";
 238                         reg = <0x620000 0x5E0000>;
 239                 };
 240         };
 241 };
 242
 243 &rtc {
 244         status = "okay";
 245 };
 246
 247 &sata {
 248         status = "okay";
 249         /* SATA OOB timing settings */
 250         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 251         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 252         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 253         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 254         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 255         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 256         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 257         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 258         phy-names = "sata-phy";
 259         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 260 };
 261
 262 /* SD1 with level shifter */
 263 &sdhci1 {
 264         status = "okay";
 265         no-1-8-v;
 266         xlnx,mio_bank = <1>;
 267         disable-wp;
 268 };
 269
 270 &serdes {
 271         status = "okay";
 272 };
 273
 274 &uart0 {
 275         status = "okay";
 276 };
 277
 278 &uart1 {
 279         status = "okay";
 280 };
 281
 282 /* ULPI SMSC USB3320 */
 283 &usb0 {
 284         status = "okay";
 285 };
 286
 287 &dwc3_0 {
 288         status = "okay";
 289         dr_mode = "host";
 290         snps,usb3_lpm_capable;
 291         phy-names = "usb3-phy";
 292         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 293         maximum-speed = "super-speed";
 294 };
 295
 296 &watchdog0 {
 297         status = "okay";
 298 };
 299
 300 &xilinx_ams {
 301         status = "okay";
 302 };
 303
 304 &ams_ps {
 305         status = "okay";
 306 };
 307
 308 &ams_pl {
 309         status = "okay";
 310 };