1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/phy/phy.h>
18 model = "ZynqMP ZCU104 RevA";
19 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
35 bootargs = "earlycon";
36 stdout-path = "serial0:115200n8";
40 device_type = "memory";
41 reg = <0x0 0x0 0x0 0x80000000>;
56 phy-mode = "rgmii-id";
59 ti,rx-internal-delay = <0x8>;
60 ti,tx-internal-delay = <0xa>;
61 ti,fifo-depth = <0x1>;
75 clock-frequency = <400000>;
77 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
78 i2c-mux@74 { /* u34 */
79 compatible = "nxp,pca9548";
88 * IIC_EEPROM 1kB memory which uses 256B blocks
89 * where every block has different address.
90 * 0 - 256B address 0x54
91 * 256B - 512B address 0x55
92 * 512B - 768B address 0x56
93 * 768B - 1024B address 0x57
95 eeprom: eeprom@54 { /* u23 */
96 compatible = "atmel,24c08";
104 #address-cells = <1>;
107 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
108 compatible = "idt,8t49n287";
114 #address-cells = <1>;
117 irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
119 compatible = "infineon,irps5401";
122 irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
124 compatible = "infineon,irps5401";
130 #address-cells = <1>;
133 tca6416_u97: gpio@20 {
134 compatible = "ti,tca6416";
141 * 0 - IRPS5401_ALERT_B
142 * 1 - HDMI_8T49N241_INT_ALM
144 * 3 - MAX6643_FANFAIL_B
145 * 5 - IIC_MUX_RESET_B
146 * 6 - GEM3_EXP_RESET_B
147 * 7 - FMC_LPC_PRSNT_M2C_B
148 * 4, 10 - 17 - not connected
154 #address-cells = <1>;
160 #address-cells = <1>;
165 /* 3, 6 not connected */
172 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
173 #address-cells = <1>;
176 spi-tx-bus-width = <1>;
177 spi-rx-bus-width = <4>;
178 spi-max-frequency = <108000000>; /* Based on DC1 spec */
179 partition@qspi-fsbl-uboot { /* for testing purpose */
180 label = "qspi-fsbl-uboot";
181 reg = <0x0 0x100000>;
183 partition@qspi-linux { /* for testing purpose */
184 label = "qspi-linux";
185 reg = <0x100000 0x500000>;
187 partition@qspi-device-tree { /* for testing purpose */
188 label = "qspi-device-tree";
189 reg = <0x600000 0x20000>;
191 partition@qspi-rootfs { /* for testing purpose */
192 label = "qspi-rootfs";
193 reg = <0x620000 0x5E0000>;
204 /* SATA OOB timing settings */
205 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
206 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
207 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
208 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
209 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
210 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
211 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
212 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
213 phy-names = "sata-phy";
214 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
217 /* SD1 with level shifter */
237 /* ULPI SMSC USB3320 */
245 snps,usb3_lpm_capable;
246 phy-names = "usb3-phy";
247 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
248 maximum-speed = "super-speed";