1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/phy/phy.h>
18 model = "ZynqMP ZCU104 RevA";
19 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
35 bootargs = "earlycon";
36 stdout-path = "serial0:115200n8";
40 device_type = "memory";
41 reg = <0x0 0x0 0x0 0x80000000>;
88 phy-mode = "rgmii-id";
89 phy0: ethernet-phy@c {
91 ti,rx-internal-delay = <0x8>;
92 ti,tx-internal-delay = <0xa>;
93 ti,fifo-depth = <0x1>;
94 ti,dp83867-rxctrl-strap-quirk;
108 clock-frequency = <400000>;
110 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
111 i2c-mux@74 { /* u34 */
112 compatible = "nxp,pca9548";
113 #address-cells = <1>;
117 #address-cells = <1>;
121 * IIC_EEPROM 1kB memory which uses 256B blocks
122 * where every block has different address.
123 * 0 - 256B address 0x54
124 * 256B - 512B address 0x55
125 * 512B - 768B address 0x56
126 * 768B - 1024B address 0x57
128 eeprom: eeprom@54 { /* u23 */
129 compatible = "atmel,24c08";
131 #address-cells = <1>;
137 #address-cells = <1>;
140 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
141 compatible = "idt,8t49n287";
147 #address-cells = <1>;
150 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
151 compatible = "infineon,irps5401";
152 reg = <0x43>; /* pmbus / i2c 0x13 */
154 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
155 compatible = "infineon,irps5401";
156 reg = <0x44>; /* pmbus / i2c 0x14 */
161 #address-cells = <1>;
164 tca6416_u97: gpio@20 {
165 compatible = "ti,tca6416";
172 * 0 - IRPS5401_ALERT_B
173 * 1 - HDMI_8T49N241_INT_ALM
175 * 3 - MAX6643_FANFAIL_B
176 * 5 - IIC_MUX_RESET_B
177 * 6 - GEM3_EXP_RESET_B
178 * 7 - FMC_LPC_PRSNT_M2C_B
179 * 4, 10 - 17 - not connected
185 #address-cells = <1>;
191 #address-cells = <1>;
196 /* 3, 6 not connected */
203 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
204 #address-cells = <1>;
207 spi-tx-bus-width = <1>;
208 spi-rx-bus-width = <4>;
209 spi-max-frequency = <108000000>; /* Based on DC1 spec */
210 partition@0 { /* for testing purpose */
211 label = "qspi-fsbl-uboot";
212 reg = <0x0 0x100000>;
214 partition@100000 { /* for testing purpose */
215 label = "qspi-linux";
216 reg = <0x100000 0x500000>;
218 partition@600000 { /* for testing purpose */
219 label = "qspi-device-tree";
220 reg = <0x600000 0x20000>;
222 partition@620000 { /* for testing purpose */
223 label = "qspi-rootfs";
224 reg = <0x620000 0x5E0000>;
235 /* SATA OOB timing settings */
236 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
237 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
238 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
239 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
240 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
241 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
242 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
243 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
244 phy-names = "sata-phy";
245 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
248 /* SD1 with level shifter */
268 /* ULPI SMSC USB3320 */
276 snps,usb3_lpm_capable;
277 phy-names = "usb3-phy";
278 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
279 maximum-speed = "super-speed";