1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/phy/phy.h>
18 model = "ZynqMP ZCU104 RevA";
19 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
35 bootargs = "earlycon";
36 stdout-path = "serial0:115200n8";
40 device_type = "memory";
41 reg = <0x0 0x0 0x0 0x80000000>;
88 phy-mode = "rgmii-id";
89 phy0: ethernet-phy@c {
91 ti,rx-internal-delay = <0x8>;
92 ti,tx-internal-delay = <0xa>;
93 ti,fifo-depth = <0x1>;
94 ti,dp83867-rxctrl-strap-quirk;
108 clock-frequency = <400000>;
110 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
111 i2c-mux@74 { /* u34 */
112 compatible = "nxp,pca9548";
113 #address-cells = <1>;
117 #address-cells = <1>;
121 * IIC_EEPROM 1kB memory which uses 256B blocks
122 * where every block has different address.
123 * 0 - 256B address 0x54
124 * 256B - 512B address 0x55
125 * 512B - 768B address 0x56
126 * 768B - 1024B address 0x57
128 eeprom: eeprom@54 { /* u23 */
129 compatible = "atmel,24c08";
131 #address-cells = <1>;
137 #address-cells = <1>;
140 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
141 compatible = "idt,8t49n287";
147 #address-cells = <1>;
150 irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
152 compatible = "infineon,irps5401";
155 irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
157 compatible = "infineon,irps5401";
163 #address-cells = <1>;
166 tca6416_u97: gpio@20 {
167 compatible = "ti,tca6416";
174 * 0 - IRPS5401_ALERT_B
175 * 1 - HDMI_8T49N241_INT_ALM
177 * 3 - MAX6643_FANFAIL_B
178 * 5 - IIC_MUX_RESET_B
179 * 6 - GEM3_EXP_RESET_B
180 * 7 - FMC_LPC_PRSNT_M2C_B
181 * 4, 10 - 17 - not connected
187 #address-cells = <1>;
193 #address-cells = <1>;
198 /* 3, 6 not connected */
205 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
206 #address-cells = <1>;
209 spi-tx-bus-width = <1>;
210 spi-rx-bus-width = <4>;
211 spi-max-frequency = <108000000>; /* Based on DC1 spec */
212 partition@0 { /* for testing purpose */
213 label = "qspi-fsbl-uboot";
214 reg = <0x0 0x100000>;
216 partition@100000 { /* for testing purpose */
217 label = "qspi-linux";
218 reg = <0x100000 0x500000>;
220 partition@600000 { /* for testing purpose */
221 label = "qspi-device-tree";
222 reg = <0x600000 0x20000>;
224 partition@620000 { /* for testing purpose */
225 label = "qspi-rootfs";
226 reg = <0x620000 0x5E0000>;
237 /* SATA OOB timing settings */
238 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
239 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
240 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
241 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
242 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
243 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
244 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
245 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
246 phy-names = "sata-phy";
247 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
250 /* SD1 with level shifter */
270 /* ULPI SMSC USB3320 */
278 snps,usb3_lpm_capable;
279 phy-names = "usb3-phy";
280 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
281 maximum-speed = "super-speed";