1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
19 model = "ZynqMP ZCU102 RevA";
20 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
39 xlnx,eeprom = &eeprom;
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
48 compatible = "gpio-keys";
52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53 linux,code = <KEY_DOWN>;
60 compatible = "gpio-leds";
63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
111 phy-handle = <&phy0>;
112 phy-mode = "rgmii-id";
115 ti,rx-internal-delay = <0x8>;
116 ti,tx-internal-delay = <0xa>;
117 ti,fifo-depth = <0x1>;
131 clock-frequency = <400000>;
133 tca6416_u97: gpio@20 {
134 compatible = "ti,tca6416";
141 * 0 - PS_GTR_LAN_SEL0
142 * 1 - PS_GTR_LAN_SEL1
143 * 2 - PS_GTR_LAN_SEL2
144 * 3 - PS_GTR_LAN_SEL3
145 * 4 - PCI_CLK_DIR_SEL
146 * 5 - IIC_MUX_RESET_B
147 * 6 - GEM3_EXP_RESET_B
148 * 7, 10 - 17 - not connected
154 output-low; /* PCIE = 0, DP = 1 */
160 output-high; /* PCIE = 0, DP = 1 */
166 output-high; /* PCIE = 0, USB0 = 1 */
172 output-high; /* PCIE = 0, SATA = 1 */
177 tca6416_u61: gpio@21 {
178 compatible = "ti,tca6416";
189 * 4 - MIO26_PMU_INPUT_LS
192 * 7 - MAXIM_PMBUS_ALERT
193 * 10 - PL_DDR4_VTERM_EN
194 * 11 - PL_DDR4_VPP_2V5_EN
195 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
196 * 13 - PS_DIMM_SUSPEND_EN
197 * 14 - PS_DDR4_VTERM_EN
198 * 15 - PS_DDR4_VPP_2V5_EN
199 * 16 - 17 - not connected
203 i2c-mux@75 { /* u60 */
204 compatible = "nxp,pca9544";
205 #address-cells = <1>;
209 #address-cells = <1>;
213 ina226@40 { /* u76 */
214 compatible = "ti,ina226";
216 shunt-resistor = <5000>;
218 ina226@41 { /* u77 */
219 compatible = "ti,ina226";
221 shunt-resistor = <5000>;
223 ina226@42 { /* u78 */
224 compatible = "ti,ina226";
226 shunt-resistor = <5000>;
228 ina226@43 { /* u87 */
229 compatible = "ti,ina226";
231 shunt-resistor = <5000>;
233 ina226@44 { /* u85 */
234 compatible = "ti,ina226";
236 shunt-resistor = <5000>;
238 ina226@45 { /* u86 */
239 compatible = "ti,ina226";
241 shunt-resistor = <5000>;
243 ina226@46 { /* u93 */
244 compatible = "ti,ina226";
246 shunt-resistor = <5000>;
248 ina226@47 { /* u88 */
249 compatible = "ti,ina226";
251 shunt-resistor = <5000>;
253 ina226@4a { /* u15 */
254 compatible = "ti,ina226";
256 shunt-resistor = <5000>;
258 ina226@4b { /* u92 */
259 compatible = "ti,ina226";
261 shunt-resistor = <5000>;
265 #address-cells = <1>;
269 ina226@40 { /* u79 */
270 compatible = "ti,ina226";
272 shunt-resistor = <2000>;
274 ina226@41 { /* u81 */
275 compatible = "ti,ina226";
277 shunt-resistor = <5000>;
279 ina226@42 { /* u80 */
280 compatible = "ti,ina226";
282 shunt-resistor = <5000>;
284 ina226@43 { /* u84 */
285 compatible = "ti,ina226";
287 shunt-resistor = <5000>;
289 ina226@44 { /* u16 */
290 compatible = "ti,ina226";
292 shunt-resistor = <5000>;
294 ina226@45 { /* u65 */
295 compatible = "ti,ina226";
297 shunt-resistor = <5000>;
299 ina226@46 { /* u74 */
300 compatible = "ti,ina226";
302 shunt-resistor = <5000>;
304 ina226@47 { /* u75 */
305 compatible = "ti,ina226";
307 shunt-resistor = <5000>;
311 #address-cells = <1>;
314 /* MAXIM_PMBUS - 00 */
315 max15301@a { /* u46 */
316 compatible = "maxim,max15301";
319 max15303@b { /* u4 */
320 compatible = "maxim,max15303";
323 max15303@10 { /* u13 */
324 compatible = "maxim,max15303";
327 max15301@13 { /* u47 */
328 compatible = "maxim,max15301";
331 max15303@14 { /* u7 */
332 compatible = "maxim,max15303";
335 max15303@15 { /* u6 */
336 compatible = "maxim,max15303";
339 max15303@16 { /* u10 */
340 compatible = "maxim,max15303";
343 max15303@17 { /* u9 */
344 compatible = "maxim,max15303";
347 max15301@18 { /* u63 */
348 compatible = "maxim,max15301";
351 max15303@1a { /* u49 */
352 compatible = "maxim,max15303";
355 max15303@1d { /* u18 */
356 compatible = "maxim,max15303";
359 max15303@20 { /* u8 */
360 compatible = "maxim,max15303";
361 status = "disabled"; /* unreachable */
364 max20751@72 { /* u95 */
365 compatible = "maxim,max20751";
368 max20751@73 { /* u96 */
369 compatible = "maxim,max20751";
373 /* Bus 3 is not connected */
379 clock-frequency = <400000>;
381 /* PL i2c via PCA9306 - u45 */
382 i2c-mux@74 { /* u34 */
383 compatible = "nxp,pca9548";
384 #address-cells = <1>;
388 #address-cells = <1>;
392 * IIC_EEPROM 1kB memory which uses 256B blocks
393 * where every block has different address.
394 * 0 - 256B address 0x54
395 * 256B - 512B address 0x55
396 * 512B - 768B address 0x56
397 * 768B - 1024B address 0x57
399 eeprom: eeprom@54 { /* u23 */
400 compatible = "atmel,24c08";
405 #address-cells = <1>;
408 si5341: clock-generator@36 { /* SI5341 - u69 */
409 compatible = "silabs,si5341";
415 #address-cells = <1>;
418 si570_1: clock-generator@5d { /* USER SI570 - u42 */
420 compatible = "silabs,si570";
422 temperature-stability = <50>;
423 factory-fout = <300000000>;
424 clock-frequency = <300000000>;
425 clock-output-names = "si570_user";
429 #address-cells = <1>;
432 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
434 compatible = "silabs,si570";
436 temperature-stability = <50>; /* copy from zc702 */
437 factory-fout = <156250000>;
438 clock-frequency = <148500000>;
439 clock-output-names = "si570_mgt";
443 #address-cells = <1>;
446 si5328: clock-generator@69 {/* SI5328 - u20 */
447 compatible = "silabs,si5328";
450 * Chip has interrupt present connected to PL
451 * interrupt-parent = <&>;
456 /* 5 - 7 unconnected */
460 compatible = "nxp,pca9548"; /* u135 */
461 #address-cells = <1>;
466 #address-cells = <1>;
472 #address-cells = <1>;
478 #address-cells = <1>;
484 #address-cells = <1>;
490 #address-cells = <1>;
496 #address-cells = <1>;
502 #address-cells = <1>;
508 #address-cells = <1>;
524 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
525 #address-cells = <1>;
528 spi-tx-bus-width = <1>;
529 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
530 spi-max-frequency = <108000000>; /* Based on DC1 spec */
531 partition@qspi-fsbl-uboot { /* for testing purpose */
532 label = "qspi-fsbl-uboot";
533 reg = <0x0 0x100000>;
535 partition@qspi-linux { /* for testing purpose */
536 label = "qspi-linux";
537 reg = <0x100000 0x500000>;
539 partition@qspi-device-tree { /* for testing purpose */
540 label = "qspi-device-tree";
541 reg = <0x600000 0x20000>;
543 partition@qspi-rootfs { /* for testing purpose */
544 label = "qspi-rootfs";
545 reg = <0x620000 0x5E0000>;
556 /* SATA OOB timing settings */
557 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
558 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
559 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
560 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
561 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
562 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
563 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
564 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
565 phy-names = "sata-phy";
566 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
569 /* SD1 with level shifter */
572 no-1-8-v; /* for 1.0 silicon */
588 /* ULPI SMSC USB3320 */
596 snps,usb3_lpm_capable;
597 phy-names = "usb3-phy";
598 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
599 maximum-speed = "super-speed";
644 &xlnx_dp_snd_codec0 {