arch/arm/dts/zynqmp-zcu102-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU102 RevA
   4  *
   5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU102 RevA";
  20         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &dcc;
  32                 spi0 = &qspi;
  33                 usb0 = &usb0;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 autorepeat;
  51                 sw19 {
  52                         label = "sw19";
  53                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  54                         linux,code = <108>; /* down */
  55                         gpio-key,wakeup;
  56                         autorepeat;
  57                 };
  58         };
  59
  60         leds {
  61                 compatible = "gpio-leds";
  62                 heartbeat_led {
  63                         label = "heartbeat";
  64                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  65                         linux,default-trigger = "heartbeat";
  66                 };
  67         };
  68 };
  69
  70 &can1 {
  71         status = "okay";
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_can1_default>;
  74 };
  75
  76 &dcc {
  77         status = "okay";
  78 };
  79
  80 &fpd_dma_chan1 {
  81         status = "okay";
  82 };
  83
  84 &fpd_dma_chan2 {
  85         status = "okay";
  86 };
  87
  88 &fpd_dma_chan3 {
  89         status = "okay";
  90 };
  91
  92 &fpd_dma_chan4 {
  93         status = "okay";
  94 };
  95
  96 &fpd_dma_chan5 {
  97         status = "okay";
  98 };
  99
 100 &fpd_dma_chan6 {
 101         status = "okay";
 102 };
 103
 104 &fpd_dma_chan7 {
 105         status = "okay";
 106 };
 107
 108 &fpd_dma_chan8 {
 109         status = "okay";
 110 };
 111
 112 &gem3 {
 113         status = "okay";
 114         phy-handle = <&phy0>;
 115         phy-mode = "rgmii-id";
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_gem3_default>;
 118         phy0: phy@21 {
 119                 reg = <21>;
 120                 ti,rx-internal-delay = <0x8>;
 121                 ti,tx-internal-delay = <0xa>;
 122                 ti,fifo-depth = <0x1>;
 123         };
 124 };
 125
 126 &gpio {
 127         status = "okay";
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&pinctrl_gpio_default>;
 130 };
 131
 132 &gpu {
 133         status = "okay";
 134 };
 135
 136 &i2c0 {
 137         status = "okay";
 138         clock-frequency = <400000>;
 139         pinctrl-names = "default", "gpio";
 140         pinctrl-0 = <&pinctrl_i2c0_default>;
 141         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 142         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 143         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 144
 145         tca6416_u97: gpio@20 {
 146                 /*
 147                  * Enable all GTs to out from U-Boot
 148                  * i2c mw 20 6 0  - setup IO to output
 149                  * i2c mw 20 2 ef - setup output values on pins 0-7
 150                  * i2c mw 20 3 ff - setup output values on pins 10-17
 151                  */
 152                 compatible = "ti,tca6416";
 153                 reg = <0x20>;
 154                 gpio-controller;
 155                 #gpio-cells = <2>;
 156                 /*
 157                  * IRQ not connected
 158                  * Lines:
 159                  * 0 - PS_GTR_LAN_SEL0
 160                  * 1 - PS_GTR_LAN_SEL1
 161                  * 2 - PS_GTR_LAN_SEL2
 162                  * 3 - PS_GTR_LAN_SEL3
 163                  * 4 - PCI_CLK_DIR_SEL
 164                  * 5 - IIC_MUX_RESET_B
 165                  * 6 - GEM3_EXP_RESET_B
 166                  * 7, 10 - 17 - not connected
 167                  */
 168
 169                 gtr_sel0 {
 170                         gpio-hog;
 171                         gpios = <0 0>;
 172                         output-low; /* PCIE = 0, DP = 1 */
 173                         line-name = "sel0";
 174                 };
 175                 gtr_sel1 {
 176                         gpio-hog;
 177                         gpios = <1 0>;
 178                         output-high; /* PCIE = 0, DP = 1 */
 179                         line-name = "sel1";
 180                 };
 181                 gtr_sel2 {
 182                         gpio-hog;
 183                         gpios = <2 0>;
 184                         output-high; /* PCIE = 0, USB0 = 1 */
 185                         line-name = "sel2";
 186                 };
 187                 gtr_sel3 {
 188                         gpio-hog;
 189                         gpios = <3 0>;
 190                         output-high; /* PCIE = 0, SATA = 1 */
 191                         line-name = "sel3";
 192                 };
 193         };
 194
 195         tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
 196                 compatible = "ti,tca6416";
 197                 reg = <0x21>;
 198                 gpio-controller;
 199                 #gpio-cells = <2>;
 200                 /*
 201                  * IRQ not connected
 202                  * Lines:
 203                  * 0 - VCCPSPLL_EN
 204                  * 1 - MGTRAVCC_EN
 205                  * 2 - MGTRAVTT_EN
 206                  * 3 - VCCPSDDRPLL_EN
 207                  * 4 - MIO26_PMU_INPUT_LS
 208                  * 5 - PL_PMBUS_ALERT
 209                  * 6 - PS_PMBUS_ALERT
 210                  * 7 - MAXIM_PMBUS_ALERT
 211                  * 10 - PL_DDR4_VTERM_EN
 212                  * 11 - PL_DDR4_VPP_2V5_EN
 213                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 214                  * 13 - PS_DIMM_SUSPEND_EN
 215                  * 14 - PS_DDR4_VTERM_EN
 216                  * 15 - PS_DDR4_VPP_2V5_EN
 217                  * 16 - 17 - not connected
 218                  */
 219         };
 220
 221         i2c-mux@75 { /* u60 */
 222                 compatible = "nxp,pca9544";
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 reg = <0x75>;
 226                 i2c@0 { /* i2c mw 75 0 1 */
 227                         #address-cells = <1>;
 228                         #size-cells = <0>;
 229                         reg = <0>;
 230                         /* PS_PMBUS */
 231                         ina226@40 { /* u76 */
 232                                 compatible = "ti,ina226";
 233                                 reg = <0x40>;
 234                                 shunt-resistor = <5000>;
 235                         };
 236                         ina226@41 { /* u77 */
 237                                 compatible = "ti,ina226";
 238                                 reg = <0x41>;
 239                                 shunt-resistor = <5000>;
 240                         };
 241                         ina226@42 { /* u78 */
 242                                 compatible = "ti,ina226";
 243                                 reg = <0x42>;
 244                                 shunt-resistor = <5000>;
 245                         };
 246                         ina226@43 { /* u87 */
 247                                 compatible = "ti,ina226";
 248                                 reg = <0x43>;
 249                                 shunt-resistor = <5000>;
 250                         };
 251                         ina226@44 { /* u85 */
 252                                 compatible = "ti,ina226";
 253                                 reg = <0x44>;
 254                                 shunt-resistor = <5000>;
 255                         };
 256                         ina226@45 { /* u86 */
 257                                 compatible = "ti,ina226";
 258                                 reg = <0x45>;
 259                                 shunt-resistor = <5000>;
 260                         };
 261                         ina226@46 { /* u93 */
 262                                 compatible = "ti,ina226";
 263                                 reg = <0x46>;
 264                                 shunt-resistor = <5000>;
 265                         };
 266                         ina226@47 { /* u88 */
 267                                 compatible = "ti,ina226";
 268                                 reg = <0x47>;
 269                                 shunt-resistor = <5000>;
 270                         };
 271                         ina226@4a { /* u15 */
 272                                 compatible = "ti,ina226";
 273                                 reg = <0x4a>;
 274                                 shunt-resistor = <5000>;
 275                         };
 276                         ina226@4b { /* u92 */
 277                                 compatible = "ti,ina226";
 278                                 reg = <0x4b>;
 279                                 shunt-resistor = <5000>;
 280                         };
 281                 };
 282                 i2c@1 { /* i2c mw 75 0 1 */
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                         reg = <1>;
 286                         /* PL_PMBUS */
 287                         ina226@40 { /* u79 */
 288                                 compatible = "ti,ina226";
 289                                 reg = <0x40>;
 290                                 shunt-resistor = <2000>;
 291                         };
 292                         ina226@41 { /* u81 */
 293                                 compatible = "ti,ina226";
 294                                 reg = <0x41>;
 295                                 shunt-resistor = <5000>;
 296                         };
 297                         ina226@42 { /* u80 */
 298                                 compatible = "ti,ina226";
 299                                 reg = <0x42>;
 300                                 shunt-resistor = <5000>;
 301                         };
 302                         ina226@43 { /* u84 */
 303                                 compatible = "ti,ina226";
 304                                 reg = <0x43>;
 305                                 shunt-resistor = <5000>;
 306                         };
 307                         ina226@44 { /* u16 */
 308                                 compatible = "ti,ina226";
 309                                 reg = <0x44>;
 310                                 shunt-resistor = <5000>;
 311                         };
 312                         ina226@45 { /* u65 */
 313                                 compatible = "ti,ina226";
 314                                 reg = <0x45>;
 315                                 shunt-resistor = <5000>;
 316                         };
 317                         ina226@46 { /* u74 */
 318                                 compatible = "ti,ina226";
 319                                 reg = <0x46>;
 320                                 shunt-resistor = <5000>;
 321                         };
 322                         ina226@47 { /* u75 */
 323                                 compatible = "ti,ina226";
 324                                 reg = <0x47>;
 325                                 shunt-resistor = <5000>;
 326                         };
 327                 };
 328                 i2c@2 { /* i2c mw 75 0 1 */
 329                         #address-cells = <1>;
 330                         #size-cells = <0>;
 331                         reg = <2>;
 332                         /* MAXIM_PMBUS - 00 */
 333                         max15301@a { /* u46 */
 334                                 compatible = "maxim,max15301";
 335                                 reg = <0xa>;
 336                         };
 337                         max15303@b { /* u4 */
 338                                 compatible = "maxim,max15303";
 339                                 reg = <0xb>;
 340                         };
 341                         max15303@10 { /* u13 */
 342                                 compatible = "maxim,max15303";
 343                                 reg = <0x10>;
 344                         };
 345                         max15301@13 { /* u47 */
 346                                 compatible = "maxim,max15301";
 347                                 reg = <0x13>;
 348                         };
 349                         max15303@14 { /* u7 */
 350                                 compatible = "maxim,max15303";
 351                                 reg = <0x14>;
 352                         };
 353                         max15303@15 { /* u6 */
 354                                 compatible = "maxim,max15303";
 355                                 reg = <0x15>;
 356                         };
 357                         max15303@16 { /* u10 */
 358                                 compatible = "maxim,max15303";
 359                                 reg = <0x16>;
 360                         };
 361                         max15303@17 { /* u9 */
 362                                 compatible = "maxim,max15303";
 363                                 reg = <0x17>;
 364                         };
 365                         max15301@18 { /* u63 */
 366                                 compatible = "maxim,max15301";
 367                                 reg = <0x18>;
 368                         };
 369                         max15303@1a { /* u49 */
 370                                 compatible = "maxim,max15303";
 371                                 reg = <0x1a>;
 372                         };
 373                         max15303@1d { /* u18 */
 374                                 compatible = "maxim,max15303";
 375                                 reg = <0x1d>;
 376                         };
 377                         max15303@20 { /* u8 */
 378                                 compatible = "maxim,max15303";
 379                                 status = "disabled"; /* unreachable */
 380                                 reg = <0x20>;
 381                         };
 382
 383                         max20751@72 { /* u95 */
 384                                 compatible = "maxim,max20751";
 385                                 reg = <0x72>;
 386                         };
 387                         max20751@73 { /* u96 */
 388                                 compatible = "maxim,max20751";
 389                                 reg = <0x73>;
 390                         };
 391                 };
 392                 /* Bus 3 is not connected */
 393         };
 394 };
 395
 396 &i2c1 {
 397         status = "okay";
 398         clock-frequency = <400000>;
 399         pinctrl-names = "default", "gpio";
 400         pinctrl-0 = <&pinctrl_i2c1_default>;
 401         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 402         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 403         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 404
 405         /* PL i2c via PCA9306 - u45 */
 406         i2c-mux@74 { /* u34 */
 407                 compatible = "nxp,pca9548";
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 reg = <0x74>;
 411                 i2c@0 { /* i2c mw 74 0 1 */
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         reg = <0>;
 415                         /*
 416                          * IIC_EEPROM 1kB memory which uses 256B blocks
 417                          * where every block has different address.
 418                          *    0 - 256B address 0x54
 419                          * 256B - 512B address 0x55
 420                          * 512B - 768B address 0x56
 421                          * 768B - 1024B address 0x57
 422                          */
 423                         eeprom: eeprom@54 { /* u23 */
 424                                 compatible = "at,24c08";
 425                                 reg = <0x54>;
 426                         };
 427                 };
 428                 i2c@1 { /* i2c mw 74 0 2 */
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         reg = <1>;
 432                         si5341: clock-generator1@36 { /* SI5341 - u69 */
 433                                 compatible = "si5341";
 434                                 reg = <0x36>;
 435                         };
 436
 437                 };
 438                 i2c@2 { /* i2c mw 74 0 4 */
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         reg = <2>;
 442                         si570_1: clock-generator2@5d { /* USER SI570 - u42 */
 443                                 #clock-cells = <0>;
 444                                 compatible = "silabs,si570";
 445                                 reg = <0x5d>;
 446                                 temperature-stability = <50>;
 447                                 factory-fout = <300000000>;
 448                                 clock-frequency = <300000000>;
 449                         };
 450                 };
 451                 i2c@3 { /* i2c mw 74 0 8 */
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         reg = <3>;
 455                         si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
 456                                 #clock-cells = <0>;
 457                                 compatible = "silabs,si570";
 458                                 reg = <0x5d>;
 459                                 temperature-stability = <50>; /* copy from zc702 */
 460                                 factory-fout = <156250000>;
 461                                 clock-frequency = <148500000>;
 462                         };
 463                 };
 464                 i2c@4 { /* i2c mw 74 0 10 */
 465                         #address-cells = <1>;
 466                         #size-cells = <0>;
 467                         reg = <4>;
 468                         si5328: clock-generator4@69 {/* SI5328 - u20 */
 469                                 compatible = "silabs,si5328";
 470                                 reg = <0x69>;
 471                                 /*
 472                                  * Chip has interrupt present connected to PL
 473                                  * interrupt-parent = <&>;
 474                                  * interrupts = <>;
 475                                  */
 476                         };
 477                 };
 478                 /* 5 - 7 unconnected */
 479         };
 480
 481         i2c-mux@75 {
 482                 compatible = "nxp,pca9548"; /* u135 */
 483                 #address-cells = <1>;
 484                 #size-cells = <0>;
 485                 reg = <0x75>;
 486
 487                 i2c@0 {
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                         reg = <0>;
 491                         /* HPC0_IIC */
 492                 };
 493                 i2c@1 {
 494                         #address-cells = <1>;
 495                         #size-cells = <0>;
 496                         reg = <1>;
 497                         /* HPC1_IIC */
 498                 };
 499                 i2c@2 {
 500                         #address-cells = <1>;
 501                         #size-cells = <0>;
 502                         reg = <2>;
 503                         /* SYSMON */
 504                 };
 505                 i2c@3 { /* i2c mw 75 0 8 */
 506                         #address-cells = <1>;
 507                         #size-cells = <0>;
 508                         reg = <3>;
 509                         /* DDR4 SODIMM */
 510                         dev@19 {
 511                                 reg = <0x19>;
 512                         };
 513                         dev@30 {
 514                                 reg = <0x30>;
 515                         };
 516                         dev@35 {
 517                                 reg = <0x35>;
 518                         };
 519                         dev@36 {
 520                                 reg = <0x36>;
 521                         };
 522                         dev@51 {
 523                                 reg = <0x51>;
 524                         };
 525                 };
 526                 i2c@4 {
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                         reg = <4>;
 530                         /* SEP 3 */
 531                 };
 532                 i2c@5 {
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                         reg = <5>;
 536                         /* SEP 2 */
 537                 };
 538                 i2c@6 {
 539                         #address-cells = <1>;
 540                         #size-cells = <0>;
 541                         reg = <6>;
 542                         /* SEP 1 */
 543                 };
 544                 i2c@7 {
 545                         #address-cells = <1>;
 546                         #size-cells = <0>;
 547                         reg = <7>;
 548                         /* SEP 0 */
 549                 };
 550         };
 551 };
 552
 553 &pinctrl0 {
 554         status = "okay";
 555         pinctrl_i2c0_default: i2c0-default {
 556                 mux {
 557                         groups = "i2c0_3_grp";
 558                         function = "i2c0";
 559                 };
 560
 561                 conf {
 562                         groups = "i2c0_3_grp";
 563                         bias-pull-up;
 564                         slew-rate = <SLEW_RATE_SLOW>;
 565                         io-standard = <IO_STANDARD_LVCMOS18>;
 566                 };
 567         };
 568
 569         pinctrl_i2c0_gpio: i2c0-gpio {
 570                 mux {
 571                         groups = "gpio0_14_grp", "gpio0_15_grp";
 572                         function = "gpio0";
 573                 };
 574
 575                 conf {
 576                         groups = "gpio0_14_grp", "gpio0_15_grp";
 577                         slew-rate = <SLEW_RATE_SLOW>;
 578                         io-standard = <IO_STANDARD_LVCMOS18>;
 579                 };
 580         };
 581
 582         pinctrl_i2c1_default: i2c1-default {
 583                 mux {
 584                         groups = "i2c1_4_grp";
 585                         function = "i2c1";
 586                 };
 587
 588                 conf {
 589                         groups = "i2c1_4_grp";
 590                         bias-pull-up;
 591                         slew-rate = <SLEW_RATE_SLOW>;
 592                         io-standard = <IO_STANDARD_LVCMOS18>;
 593                 };
 594         };
 595
 596         pinctrl_i2c1_gpio: i2c1-gpio {
 597                 mux {
 598                         groups = "gpio0_16_grp", "gpio0_17_grp";
 599                         function = "gpio0";
 600                 };
 601
 602                 conf {
 603                         groups = "gpio0_16_grp", "gpio0_17_grp";
 604                         slew-rate = <SLEW_RATE_SLOW>;
 605                         io-standard = <IO_STANDARD_LVCMOS18>;
 606                 };
 607         };
 608
 609         pinctrl_uart0_default: uart0-default {
 610                 mux {
 611                         groups = "uart0_4_grp";
 612                         function = "uart0";
 613                 };
 614
 615                 conf {
 616                         groups = "uart0_4_grp";
 617                         slew-rate = <SLEW_RATE_SLOW>;
 618                         io-standard = <IO_STANDARD_LVCMOS18>;
 619                 };
 620
 621                 conf-rx {
 622                         pins = "MIO18";
 623                         bias-high-impedance;
 624                 };
 625
 626                 conf-tx {
 627                         pins = "MIO19";
 628                         bias-disable;
 629                 };
 630         };
 631
 632         pinctrl_uart1_default: uart1-default {
 633                 mux {
 634                         groups = "uart1_5_grp";
 635                         function = "uart1";
 636                 };
 637
 638                 conf {
 639                         groups = "uart1_5_grp";
 640                         slew-rate = <SLEW_RATE_SLOW>;
 641                         io-standard = <IO_STANDARD_LVCMOS18>;
 642                 };
 643
 644                 conf-rx {
 645                         pins = "MIO21";
 646                         bias-high-impedance;
 647                 };
 648
 649                 conf-tx {
 650                         pins = "MIO20";
 651                         bias-disable;
 652                 };
 653         };
 654
 655         pinctrl_usb0_default: usb0-default {
 656                 mux {
 657                         groups = "usb0_0_grp";
 658                         function = "usb0";
 659                 };
 660
 661                 conf {
 662                         groups = "usb0_0_grp";
 663                         slew-rate = <SLEW_RATE_SLOW>;
 664                         io-standard = <IO_STANDARD_LVCMOS18>;
 665                 };
 666
 667                 conf-rx {
 668                         pins = "MIO52", "MIO53", "MIO55";
 669                         bias-high-impedance;
 670                 };
 671
 672                 conf-tx {
 673                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 674                                "MIO60", "MIO61", "MIO62", "MIO63";
 675                         bias-disable;
 676                 };
 677         };
 678
 679         pinctrl_gem3_default: gem3-default {
 680                 mux {
 681                         function = "ethernet3";
 682                         groups = "ethernet3_0_grp";
 683                 };
 684
 685                 conf {
 686                         groups = "ethernet3_0_grp";
 687                         slew-rate = <SLEW_RATE_SLOW>;
 688                         io-standard = <IO_STANDARD_LVCMOS18>;
 689                 };
 690
 691                 conf-rx {
 692                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 693                                                                         "MIO75";
 694                         bias-high-impedance;
 695                         low-power-disable;
 696                 };
 697
 698                 conf-tx {
 699                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 700                                                                         "MIO69";
 701                         bias-disable;
 702                         low-power-enable;
 703                 };
 704
 705                 mux-mdio {
 706                         function = "mdio3";
 707                         groups = "mdio3_0_grp";
 708                 };
 709
 710                 conf-mdio {
 711                         groups = "mdio3_0_grp";
 712                         slew-rate = <SLEW_RATE_SLOW>;
 713                         io-standard = <IO_STANDARD_LVCMOS18>;
 714                         bias-disable;
 715                 };
 716         };
 717
 718         pinctrl_can1_default: can1-default {
 719                 mux {
 720                         function = "can1";
 721                         groups = "can1_6_grp";
 722                 };
 723
 724                 conf {
 725                         groups = "can1_6_grp";
 726                         slew-rate = <SLEW_RATE_SLOW>;
 727                         io-standard = <IO_STANDARD_LVCMOS18>;
 728                 };
 729
 730                 conf-rx {
 731                         pins = "MIO25";
 732                         bias-high-impedance;
 733                 };
 734
 735                 conf-tx {
 736                         pins = "MIO24";
 737                         bias-disable;
 738                 };
 739         };
 740
 741         pinctrl_sdhci1_default: sdhci1-default {
 742                 mux {
 743                         groups = "sdio1_0_grp";
 744                         function = "sdio1";
 745                 };
 746
 747                 conf {
 748                         groups = "sdio1_0_grp";
 749                         slew-rate = <SLEW_RATE_SLOW>;
 750                         io-standard = <IO_STANDARD_LVCMOS18>;
 751                         bias-disable;
 752                 };
 753
 754                 mux-cd {
 755                         groups = "sdio1_0_cd_grp";
 756                         function = "sdio1_cd";
 757                 };
 758
 759                 conf-cd {
 760                         groups = "sdio1_0_cd_grp";
 761                         bias-high-impedance;
 762                         bias-pull-up;
 763                         slew-rate = <SLEW_RATE_SLOW>;
 764                         io-standard = <IO_STANDARD_LVCMOS18>;
 765                 };
 766
 767                 mux-wp {
 768                         groups = "sdio1_0_wp_grp";
 769                         function = "sdio1_wp";
 770                 };
 771
 772                 conf-wp {
 773                         groups = "sdio1_0_wp_grp";
 774                         bias-high-impedance;
 775                         bias-pull-up;
 776                         slew-rate = <SLEW_RATE_SLOW>;
 777                         io-standard = <IO_STANDARD_LVCMOS18>;
 778                 };
 779         };
 780
 781         pinctrl_gpio_default: gpio-default {
 782                 mux-sw {
 783                         function = "gpio0";
 784                         groups = "gpio0_22_grp", "gpio0_23_grp";
 785                 };
 786
 787                 conf-sw {
 788                         groups = "gpio0_22_grp", "gpio0_23_grp";
 789                         slew-rate = <SLEW_RATE_SLOW>;
 790                         io-standard = <IO_STANDARD_LVCMOS18>;
 791                 };
 792
 793                 mux-msp {
 794                         function = "gpio0";
 795                         groups = "gpio0_13_grp", "gpio0_38_grp";
 796                 };
 797
 798                 conf-msp {
 799                         groups = "gpio0_13_grp", "gpio0_38_grp";
 800                         slew-rate = <SLEW_RATE_SLOW>;
 801                         io-standard = <IO_STANDARD_LVCMOS18>;
 802                 };
 803
 804                 conf-pull-up {
 805                         pins = "MIO22", "MIO23";
 806                         bias-pull-up;
 807                 };
 808
 809                 conf-pull-none {
 810                         pins = "MIO13", "MIO38";
 811                         bias-disable;
 812                 };
 813         };
 814 };
 815
 816 &pcie {
 817         status = "okay";
 818 };
 819
 820 &qspi {
 821         status = "okay";
 822         is-dual = <1>;
 823         flash@0 {
 824                 compatible = "m25p80"; /* 32MB */
 825                 #address-cells = <1>;
 826                 #size-cells = <1>;
 827                 reg = <0x0>;
 828                 spi-tx-bus-width = <1>;
 829                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 830                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 831                 partition@qspi-fsbl-uboot { /* for testing purpose */
 832                         label = "qspi-fsbl-uboot";
 833                         reg = <0x0 0x100000>;
 834                 };
 835                 partition@qspi-linux { /* for testing purpose */
 836                         label = "qspi-linux";
 837                         reg = <0x100000 0x500000>;
 838                 };
 839                 partition@qspi-device-tree { /* for testing purpose */
 840                         label = "qspi-device-tree";
 841                         reg = <0x600000 0x20000>;
 842                 };
 843                 partition@qspi-rootfs { /* for testing purpose */
 844                         label = "qspi-rootfs";
 845                         reg = <0x620000 0x5E0000>;
 846                 };
 847         };
 848 };
 849
 850 &rtc {
 851         status = "okay";
 852 };
 853
 854 &sata {
 855         status = "okay";
 856         /* SATA OOB timing settings */
 857         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 858         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 859         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 860         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 861         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 862         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 863         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 864         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 865         phy-names = "sata-phy";
 866         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 867 };
 868
 869 /* SD1 with level shifter */
 870 &sdhci1 {
 871         status = "okay";
 872         pinctrl-names = "default";
 873         pinctrl-0 = <&pinctrl_sdhci1_default>;
 874         no-1-8-v;       /* for 1.0 silicon */
 875         xlnx,mio_bank = <1>;
 876 };
 877
 878 &serdes {
 879         status = "okay";
 880 };
 881
 882 &uart0 {
 883         status = "okay";
 884         pinctrl-names = "default";
 885         pinctrl-0 = <&pinctrl_uart0_default>;
 886 };
 887
 888 &uart1 {
 889         status = "okay";
 890         pinctrl-names = "default";
 891         pinctrl-0 = <&pinctrl_uart1_default>;
 892 };
 893
 894 /* ULPI SMSC USB3320 */
 895 &usb0 {
 896         status = "okay";
 897         pinctrl-names = "default";
 898         pinctrl-0 = <&pinctrl_usb0_default>;
 899 };
 900
 901 &dwc3_0 {
 902         status = "okay";
 903         dr_mode = "host";
 904         snps,usb3_lpm_capable;
 905         phy-names = "usb3-phy";
 906         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 907         maximum-speed = "super-speed";
 908 };
 909
 910 &watchdog0 {
 911         status = "okay";
 912 };
 913
 914 &xilinx_ams {
 915         status = "okay";
 916 };
 917
 918 &ams_ps {
 919         status = "okay";
 920 };
 921
 922 &ams_pl {
 923         status = "okay";
 924 };
 925
 926 &xilinx_drm {
 927         status = "okay";
 928         clocks = <&si570_1>;
 929 };
 930
 931 &xlnx_dp {
 932         status = "okay";
 933 };
 934
 935 &xlnx_dp_sub {
 936         status = "okay";
 937         xlnx,vid-clk-pl;
 938 };
 939
 940 &xlnx_dp_snd_pcm0 {
 941         status = "okay";
 942 };
 943
 944 &xlnx_dp_snd_pcm1 {
 945         status = "okay";
 946 };
 947
 948 &xlnx_dp_snd_card {
 949         status = "okay";
 950 };
 951
 952 &xlnx_dp_snd_codec0 {
 953         status = "okay";
 954 };
 955
 956 &xlnx_dpdma {
 957         status = "okay";
 958 };