arch/arm/dts/zynqmp-zcu102-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU102 RevA
   4  *
   5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU102 RevA";
  20         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &dcc;
  32                 spi0 = &qspi;
  33                 usb0 = &usb0;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39                 xlnx,eeprom = &eeprom;
  40         };
  41
  42         memory@0 {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 autorepeat;
  50                 sw19 {
  51                         label = "sw19";
  52                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  53                         linux,code = <KEY_DOWN>;
  54                         gpio-key,wakeup;
  55                         autorepeat;
  56                 };
  57         };
  58
  59         leds {
  60                 compatible = "gpio-leds";
  61                 heartbeat_led {
  62                         label = "heartbeat";
  63                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  64                         linux,default-trigger = "heartbeat";
  65                 };
  66         };
  67 };
  68
  69 &can1 {
  70         status = "okay";
  71 };
  72
  73 &dcc {
  74         status = "okay";
  75 };
  76
  77 &fpd_dma_chan1 {
  78         status = "okay";
  79 };
  80
  81 &fpd_dma_chan2 {
  82         status = "okay";
  83 };
  84
  85 &fpd_dma_chan3 {
  86         status = "okay";
  87 };
  88
  89 &fpd_dma_chan4 {
  90         status = "okay";
  91 };
  92
  93 &fpd_dma_chan5 {
  94         status = "okay";
  95 };
  96
  97 &fpd_dma_chan6 {
  98         status = "okay";
  99 };
 100
 101 &fpd_dma_chan7 {
 102         status = "okay";
 103 };
 104
 105 &fpd_dma_chan8 {
 106         status = "okay";
 107 };
 108
 109 &gem3 {
 110         status = "okay";
 111         phy-handle = <&phy0>;
 112         phy-mode = "rgmii-id";
 113         phy0: ethernet-phy@21 {
 114                 reg = <21>;
 115                 ti,rx-internal-delay = <0x8>;
 116                 ti,tx-internal-delay = <0xa>;
 117                 ti,fifo-depth = <0x1>;
 118         };
 119 };
 120
 121 &gpio {
 122         status = "okay";
 123 };
 124
 125 &gpu {
 126         status = "okay";
 127 };
 128
 129 &i2c0 {
 130         status = "okay";
 131         clock-frequency = <400000>;
 132
 133         tca6416_u97: gpio@20 {
 134                 compatible = "ti,tca6416";
 135                 reg = <0x20>;
 136                 gpio-controller;
 137                 #gpio-cells = <2>;
 138                 /*
 139                  * IRQ not connected
 140                  * Lines:
 141                  * 0 - PS_GTR_LAN_SEL0
 142                  * 1 - PS_GTR_LAN_SEL1
 143                  * 2 - PS_GTR_LAN_SEL2
 144                  * 3 - PS_GTR_LAN_SEL3
 145                  * 4 - PCI_CLK_DIR_SEL
 146                  * 5 - IIC_MUX_RESET_B
 147                  * 6 - GEM3_EXP_RESET_B
 148                  * 7, 10 - 17 - not connected
 149                  */
 150
 151                 gtr_sel0 {
 152                         gpio-hog;
 153                         gpios = <0 0>;
 154                         output-low; /* PCIE = 0, DP = 1 */
 155                         line-name = "sel0";
 156                 };
 157                 gtr_sel1 {
 158                         gpio-hog;
 159                         gpios = <1 0>;
 160                         output-high; /* PCIE = 0, DP = 1 */
 161                         line-name = "sel1";
 162                 };
 163                 gtr_sel2 {
 164                         gpio-hog;
 165                         gpios = <2 0>;
 166                         output-high; /* PCIE = 0, USB0 = 1 */
 167                         line-name = "sel2";
 168                 };
 169                 gtr_sel3 {
 170                         gpio-hog;
 171                         gpios = <3 0>;
 172                         output-high; /* PCIE = 0, SATA = 1 */
 173                         line-name = "sel3";
 174                 };
 175         };
 176
 177         tca6416_u61: gpio@21 {
 178                 compatible = "ti,tca6416";
 179                 reg = <0x21>;
 180                 gpio-controller;
 181                 #gpio-cells = <2>;
 182                 /*
 183                  * IRQ not connected
 184                  * Lines:
 185                  * 0 - VCCPSPLL_EN
 186                  * 1 - MGTRAVCC_EN
 187                  * 2 - MGTRAVTT_EN
 188                  * 3 - VCCPSDDRPLL_EN
 189                  * 4 - MIO26_PMU_INPUT_LS
 190                  * 5 - PL_PMBUS_ALERT
 191                  * 6 - PS_PMBUS_ALERT
 192                  * 7 - MAXIM_PMBUS_ALERT
 193                  * 10 - PL_DDR4_VTERM_EN
 194                  * 11 - PL_DDR4_VPP_2V5_EN
 195                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 196                  * 13 - PS_DIMM_SUSPEND_EN
 197                  * 14 - PS_DDR4_VTERM_EN
 198                  * 15 - PS_DDR4_VPP_2V5_EN
 199                  * 16 - 17 - not connected
 200                  */
 201         };
 202
 203         i2c-mux@75 { /* u60 */
 204                 compatible = "nxp,pca9544";
 205                 #address-cells = <1>;
 206                 #size-cells = <0>;
 207                 reg = <0x75>;
 208                 i2c@0 {
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                         reg = <0>;
 212                         /* PS_PMBUS */
 213                         ina226@40 { /* u76 */
 214                                 compatible = "ti,ina226";
 215                                 reg = <0x40>;
 216                                 shunt-resistor = <5000>;
 217                         };
 218                         ina226@41 { /* u77 */
 219                                 compatible = "ti,ina226";
 220                                 reg = <0x41>;
 221                                 shunt-resistor = <5000>;
 222                         };
 223                         ina226@42 { /* u78 */
 224                                 compatible = "ti,ina226";
 225                                 reg = <0x42>;
 226                                 shunt-resistor = <5000>;
 227                         };
 228                         ina226@43 { /* u87 */
 229                                 compatible = "ti,ina226";
 230                                 reg = <0x43>;
 231                                 shunt-resistor = <5000>;
 232                         };
 233                         ina226@44 { /* u85 */
 234                                 compatible = "ti,ina226";
 235                                 reg = <0x44>;
 236                                 shunt-resistor = <5000>;
 237                         };
 238                         ina226@45 { /* u86 */
 239                                 compatible = "ti,ina226";
 240                                 reg = <0x45>;
 241                                 shunt-resistor = <5000>;
 242                         };
 243                         ina226@46 { /* u93 */
 244                                 compatible = "ti,ina226";
 245                                 reg = <0x46>;
 246                                 shunt-resistor = <5000>;
 247                         };
 248                         ina226@47 { /* u88 */
 249                                 compatible = "ti,ina226";
 250                                 reg = <0x47>;
 251                                 shunt-resistor = <5000>;
 252                         };
 253                         ina226@4a { /* u15 */
 254                                 compatible = "ti,ina226";
 255                                 reg = <0x4a>;
 256                                 shunt-resistor = <5000>;
 257                         };
 258                         ina226@4b { /* u92 */
 259                                 compatible = "ti,ina226";
 260                                 reg = <0x4b>;
 261                                 shunt-resistor = <5000>;
 262                         };
 263                 };
 264                 i2c@1 {
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         reg = <1>;
 268                         /* PL_PMBUS */
 269                         ina226@40 { /* u79 */
 270                                 compatible = "ti,ina226";
 271                                 reg = <0x40>;
 272                                 shunt-resistor = <2000>;
 273                         };
 274                         ina226@41 { /* u81 */
 275                                 compatible = "ti,ina226";
 276                                 reg = <0x41>;
 277                                 shunt-resistor = <5000>;
 278                         };
 279                         ina226@42 { /* u80 */
 280                                 compatible = "ti,ina226";
 281                                 reg = <0x42>;
 282                                 shunt-resistor = <5000>;
 283                         };
 284                         ina226@43 { /* u84 */
 285                                 compatible = "ti,ina226";
 286                                 reg = <0x43>;
 287                                 shunt-resistor = <5000>;
 288                         };
 289                         ina226@44 { /* u16 */
 290                                 compatible = "ti,ina226";
 291                                 reg = <0x44>;
 292                                 shunt-resistor = <5000>;
 293                         };
 294                         ina226@45 { /* u65 */
 295                                 compatible = "ti,ina226";
 296                                 reg = <0x45>;
 297                                 shunt-resistor = <5000>;
 298                         };
 299                         ina226@46 { /* u74 */
 300                                 compatible = "ti,ina226";
 301                                 reg = <0x46>;
 302                                 shunt-resistor = <5000>;
 303                         };
 304                         ina226@47 { /* u75 */
 305                                 compatible = "ti,ina226";
 306                                 reg = <0x47>;
 307                                 shunt-resistor = <5000>;
 308                         };
 309                 };
 310                 i2c@2 {
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         reg = <2>;
 314                         /* MAXIM_PMBUS - 00 */
 315                         max15301@a { /* u46 */
 316                                 compatible = "maxim,max15301";
 317                                 reg = <0xa>;
 318                         };
 319                         max15303@b { /* u4 */
 320                                 compatible = "maxim,max15303";
 321                                 reg = <0xb>;
 322                         };
 323                         max15303@10 { /* u13 */
 324                                 compatible = "maxim,max15303";
 325                                 reg = <0x10>;
 326                         };
 327                         max15301@13 { /* u47 */
 328                                 compatible = "maxim,max15301";
 329                                 reg = <0x13>;
 330                         };
 331                         max15303@14 { /* u7 */
 332                                 compatible = "maxim,max15303";
 333                                 reg = <0x14>;
 334                         };
 335                         max15303@15 { /* u6 */
 336                                 compatible = "maxim,max15303";
 337                                 reg = <0x15>;
 338                         };
 339                         max15303@16 { /* u10 */
 340                                 compatible = "maxim,max15303";
 341                                 reg = <0x16>;
 342                         };
 343                         max15303@17 { /* u9 */
 344                                 compatible = "maxim,max15303";
 345                                 reg = <0x17>;
 346                         };
 347                         max15301@18 { /* u63 */
 348                                 compatible = "maxim,max15301";
 349                                 reg = <0x18>;
 350                         };
 351                         max15303@1a { /* u49 */
 352                                 compatible = "maxim,max15303";
 353                                 reg = <0x1a>;
 354                         };
 355                         max15303@1d { /* u18 */
 356                                 compatible = "maxim,max15303";
 357                                 reg = <0x1d>;
 358                         };
 359                         max15303@20 { /* u8 */
 360                                 compatible = "maxim,max15303";
 361                                 status = "disabled"; /* unreachable */
 362                                 reg = <0x20>;
 363                         };
 364                         max20751@72 { /* u95 */
 365                                 compatible = "maxim,max20751";
 366                                 reg = <0x72>;
 367                         };
 368                         max20751@73 { /* u96 */
 369                                 compatible = "maxim,max20751";
 370                                 reg = <0x73>;
 371                         };
 372                 };
 373                 /* Bus 3 is not connected */
 374         };
 375 };
 376
 377 &i2c1 {
 378         status = "okay";
 379         clock-frequency = <400000>;
 380
 381         /* PL i2c via PCA9306 - u45 */
 382         i2c-mux@74 { /* u34 */
 383                 compatible = "nxp,pca9548";
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 reg = <0x74>;
 387                 i2c@0 {
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390                         reg = <0>;
 391                         /*
 392                          * IIC_EEPROM 1kB memory which uses 256B blocks
 393                          * where every block has different address.
 394                          *    0 - 256B address 0x54
 395                          * 256B - 512B address 0x55
 396                          * 512B - 768B address 0x56
 397                          * 768B - 1024B address 0x57
 398                          */
 399                         eeprom: eeprom@54 { /* u23 */
 400                                 compatible = "atmel,24c08";
 401                                 reg = <0x54>;
 402                         };
 403                 };
 404                 i2c@1 {
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                         reg = <1>;
 408                         si5341: clock-generator@36 { /* SI5341 - u69 */
 409                                 compatible = "silabs,si5341";
 410                                 reg = <0x36>;
 411                         };
 412
 413                 };
 414                 i2c@2 {
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         reg = <2>;
 418                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
 419                                 #clock-cells = <0>;
 420                                 compatible = "silabs,si570";
 421                                 reg = <0x5d>;
 422                                 temperature-stability = <50>;
 423                                 factory-fout = <300000000>;
 424                                 clock-frequency = <300000000>;
 425                                 clock-output-names = "si570_user";
 426                         };
 427                 };
 428                 i2c@3 {
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         reg = <3>;
 432                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
 433                                 #clock-cells = <0>;
 434                                 compatible = "silabs,si570";
 435                                 reg = <0x5d>;
 436                                 temperature-stability = <50>; /* copy from zc702 */
 437                                 factory-fout = <156250000>;
 438                                 clock-frequency = <148500000>;
 439                                 clock-output-names = "si570_mgt";
 440                         };
 441                 };
 442                 i2c@4 {
 443                         #address-cells = <1>;
 444                         #size-cells = <0>;
 445                         reg = <4>;
 446                         si5328: clock-generator@69 {/* SI5328 - u20 */
 447                                 compatible = "silabs,si5328";
 448                                 reg = <0x69>;
 449                                 /*
 450                                  * Chip has interrupt present connected to PL
 451                                  * interrupt-parent = <&>;
 452                                  * interrupts = <>;
 453                                  */
 454                         };
 455                 };
 456                 /* 5 - 7 unconnected */
 457         };
 458
 459         i2c-mux@75 {
 460                 compatible = "nxp,pca9548"; /* u135 */
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 reg = <0x75>;
 464
 465                 i2c@0 {
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                         reg = <0>;
 469                         /* HPC0_IIC */
 470                 };
 471                 i2c@1 {
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                         reg = <1>;
 475                         /* HPC1_IIC */
 476                 };
 477                 i2c@2 {
 478                         #address-cells = <1>;
 479                         #size-cells = <0>;
 480                         reg = <2>;
 481                         /* SYSMON */
 482                 };
 483                 i2c@3 {
 484                         #address-cells = <1>;
 485                         #size-cells = <0>;
 486                         reg = <3>;
 487                         /* DDR4 SODIMM */
 488                 };
 489                 i2c@4 {
 490                         #address-cells = <1>;
 491                         #size-cells = <0>;
 492                         reg = <4>;
 493                         /* SEP 3 */
 494                 };
 495                 i2c@5 {
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         reg = <5>;
 499                         /* SEP 2 */
 500                 };
 501                 i2c@6 {
 502                         #address-cells = <1>;
 503                         #size-cells = <0>;
 504                         reg = <6>;
 505                         /* SEP 1 */
 506                 };
 507                 i2c@7 {
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510                         reg = <7>;
 511                         /* SEP 0 */
 512                 };
 513         };
 514 };
 515
 516 &pcie {
 517         status = "okay";
 518 };
 519
 520 &qspi {
 521         status = "okay";
 522         is-dual = <1>;
 523         flash@0 {
 524                 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
 525                 #address-cells = <1>;
 526                 #size-cells = <1>;
 527                 reg = <0x0>;
 528                 spi-tx-bus-width = <1>;
 529                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 530                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 531                 partition@qspi-fsbl-uboot { /* for testing purpose */
 532                         label = "qspi-fsbl-uboot";
 533                         reg = <0x0 0x100000>;
 534                 };
 535                 partition@qspi-linux { /* for testing purpose */
 536                         label = "qspi-linux";
 537                         reg = <0x100000 0x500000>;
 538                 };
 539                 partition@qspi-device-tree { /* for testing purpose */
 540                         label = "qspi-device-tree";
 541                         reg = <0x600000 0x20000>;
 542                 };
 543                 partition@qspi-rootfs { /* for testing purpose */
 544                         label = "qspi-rootfs";
 545                         reg = <0x620000 0x5E0000>;
 546                 };
 547         };
 548 };
 549
 550 &rtc {
 551         status = "okay";
 552 };
 553
 554 &sata {
 555         status = "okay";
 556         /* SATA OOB timing settings */
 557         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 558         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 559         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 560         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 561         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 562         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 563         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 564         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 565         phy-names = "sata-phy";
 566         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 567 };
 568
 569 /* SD1 with level shifter */
 570 &sdhci1 {
 571         status = "okay";
 572         no-1-8-v;       /* for 1.0 silicon */
 573         xlnx,mio_bank = <1>;
 574 };
 575
 576 &serdes {
 577         status = "okay";
 578 };
 579
 580 &uart0 {
 581         status = "okay";
 582 };
 583
 584 &uart1 {
 585         status = "okay";
 586 };
 587
 588 /* ULPI SMSC USB3320 */
 589 &usb0 {
 590         status = "okay";
 591 };
 592
 593 &dwc3_0 {
 594         status = "okay";
 595         dr_mode = "host";
 596         snps,usb3_lpm_capable;
 597         phy-names = "usb3-phy";
 598         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 599         maximum-speed = "super-speed";
 600 };
 601
 602 &watchdog0 {
 603         status = "okay";
 604 };
 605
 606 &xilinx_ams {
 607         status = "okay";
 608 };
 609
 610 &ams_ps {
 611         status = "okay";
 612 };
 613
 614 &ams_pl {
 615         status = "okay";
 616 };
 617
 618 &xilinx_drm {
 619         status = "okay";
 620         clocks = <&si570_1>;
 621 };
 622
 623 &xlnx_dp {
 624         status = "okay";
 625 };
 626
 627 &xlnx_dp_sub {
 628         status = "okay";
 629         xlnx,vid-clk-pl;
 630 };
 631
 632 &xlnx_dp_snd_pcm0 {
 633         status = "okay";
 634 };
 635
 636 &xlnx_dp_snd_pcm1 {
 637         status = "okay";
 638 };
 639
 640 &xlnx_dp_snd_card {
 641         status = "okay";
 642 };
 643
 644 &xlnx_dp_snd_codec0 {
 645         status = "okay";
 646 };
 647
 648 &xlnx_dpdma {
 649         status = "okay";
 650 };