1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
54 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
129 phy-mode = "rgmii-id";
130 phy-handle = <ðernet_phy0>;
131 ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
134 ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
137 ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
140 ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
147 phy-mode = "rgmii-id";
148 phy-handle = <ðernet_phy7>;
153 phy-mode = "rgmii-id";
154 phy-handle = <ðernet_phy3>;
159 phy-mode = "rgmii-id";
160 phy-handle = <ðernet_phy8>;
172 clock-frequency = <400000>;
177 clock-frequency = <400000>;