1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx Versal a2197 RevA System Controller
5 * (C) Copyright 2019, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
11 #include "zynqmp.dtsi"
12 #include "zynqmp-clk-ccf.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
16 model = "Versal System Controller on a2197 Memory Char board RevA";
17 compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA",
18 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
39 xlnx,eeprom = <&eeprom>;
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
48 compatible = "iio-hwmon";
49 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
52 compatible = "iio-hwmon";
53 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
56 compatible = "iio-hwmon";
57 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
60 compatible = "iio-hwmon";
61 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
64 compatible = "iio-hwmon";
65 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
68 compatible = "iio-hwmon";
69 io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;
77 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
81 spi-tx-bus-width = <1>;
82 spi-rx-bus-width = <4>;
83 spi-max-frequency = <108000000>;
87 &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
92 xlnx,mio_bank = <0>; /* FIXME tap delay */
95 &uart0 { /* uart0 MIO38-39 */
100 &uart1 { /* uart1 MIO40-41 */
105 &sdhci1 { /* sd1 MIO45-51 cd in place */
114 phy-handle = <&phy0>;
115 phy-mode = "sgmii"; /* DTG generates this properly 1512 */
116 phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
117 phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
119 /* xlnx,phy-type = <PHY_TYPE_SGMII>; */
121 /* phy-names = "...";
122 phys = <&lane0 PHY_TYPE_SGMII ... >
123 Note: lane0 sgmii/lane1 usb3 */
128 gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
129 "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
130 "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
131 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
132 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
133 "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
134 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
135 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
136 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
137 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
138 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
139 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
140 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
141 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
142 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
143 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
144 "", "", "", "", "", /* 78 - 79 */
145 "", "", "", "", "", /* 80 - 84 */
146 "", "", "", "", "", /* 85 -89 */
147 "", "", "", "", "", /* 90 - 94 */
148 "", "", "", "", "", /* 95 - 99 */
149 "", "", "", "", "", /* 100 - 104 */
150 "", "", "", "", "", /* 105 - 109 */
151 "", "", "", "", "", /* 110 - 114 */
152 "", "", "", "", "", /* 115 - 119 */
153 "", "", "", "", "", /* 120 - 124 */
154 "", "", "", "", "", /* 125 - 129 */
155 "", "", "", "", "", /* 130 - 134 */
156 "", "", "", "", "", /* 135 - 139 */
157 "", "", "", "", "", /* 140 - 144 */
158 "", "", "", "", "", /* 145 - 149 */
159 "", "", "", "", "", /* 150 - 154 */
160 "", "", "", "", "", /* 155 - 159 */
161 "", "", "", "", "", /* 160 - 164 */
162 "", "", "", "", "", /* 165 - 169 */
163 "", "", "", ""; /* 170 - 174 */
166 &i2c0 { /* MIO 34-35 - can't stay here */
168 clock-frequency = <400000>;
169 i2c-mux@74 { /* u46 */
170 compatible = "nxp,pca9548";
171 #address-cells = <1>;
174 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
175 i2c@0 { /* PMBUS must be enabled via SW21 */
176 #address-cells = <1>;
179 reg_vcc1v2_lp4: tps544@15 { /* u97 */
180 compatible = "ti,tps544b25";
183 reg_vcc1v1_lp4: tps544@16 { /* u95 */
184 compatible = "ti,tps544b25";
187 reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
188 compatible = "ti,tps544b25";
191 /* UTIL_PMBUS connection */
192 reg_vcc1v8: tps544@13 { /* u92 */
193 compatible = "ti,tps544b25";
196 reg_vcc3v3: tps544@14 { /* u93 */
197 compatible = "ti,tps544b25";
200 reg_vcc5v0: tps544@1e { /* u94 */
201 compatible = "ti,tps544b25";
205 i2c@1 { /* PMBUS_INA226 */
206 #address-cells = <1>;
209 vcc_aux: ina226@42 { /* u86 */
210 compatible = "ti,ina226";
211 #io-channel-cells = <1>;
212 label = "ina226-vcc-aux";
214 shunt-resistor = <5000>;
216 vcc_ram: ina226@43 { /* u81 */
217 compatible = "ti,ina226";
218 #io-channel-cells = <1>;
219 label = "ina226-vcc-ram";
221 shunt-resistor = <5000>;
223 vcc1v1_lp4: ina226@46 { /* u96 */
224 compatible = "ti,ina226";
225 #io-channel-cells = <1>;
226 label = "ina226-vcc1v1-lp4";
228 shunt-resistor = <5000>;
230 vcc1v2_lp4: ina226@47 { /* u98 */
231 compatible = "ti,ina226";
232 #io-channel-cells = <1>;
233 label = "ina226-vcc1v2-lp4";
235 shunt-resistor = <5000>;
237 vdd1_1v8_lp4: ina226@48 { /* u100 */
238 compatible = "ti,ina226";
239 #io-channel-cells = <1>;
240 label = "ina226-vdd1-1v8-lp4";
242 shunt-resistor = <5000>;
244 vcc0v6_lp4: ina226@49 { /* u101 */
245 compatible = "ti,ina226";
246 #io-channel-cells = <1>;
247 label = "ina226-vcc0v6-lp4";
249 shunt-resistor = <5000>;
253 #address-cells = <1>;
256 reg_vccint: tps53681@c0 { /* u69 */
257 compatible = "ti,tps53681", "ti,tps53679";
260 reg_vcc_pmc: tps544@7 { /* u80 */
261 compatible = "ti,tps544b25";
264 reg_vcc_ram: tps544@8 { /* u82 */
265 compatible = "ti,tps544b25";
268 reg_vcc_pslp: tps544@9 { /* u83 */
269 compatible = "ti,tps544b25";
272 reg_vcc_psfp: tps544@a { /* u84 */
273 compatible = "ti,tps544b25";
276 reg_vccaux: tps544@d { /* u85 */
277 compatible = "ti,tps544b25";
280 reg_vccaux_pmc: tps544@e { /* u87 */
281 compatible = "ti,tps544b25";
284 reg_vcco_500: tps544@f { /* u88 */
285 compatible = "ti,tps544b25";
288 reg_vcco_501: tps544@10 { /* u89 */
289 compatible = "ti,tps544b25";
292 reg_vcco_502: tps544@11 { /* u90 */
293 compatible = "ti,tps544b25";
296 reg_vcco_503: tps544@12 { /* u91 */
297 compatible = "ti,tps544b25";
301 i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
302 #address-cells = <1>;
306 i2c@4 { /* LP_I2C_SM */
307 #address-cells = <1>;
310 /* connected to U20G */
316 /* TODO sysctrl via J239 */
317 /* TODO samtec J212G/H via J242 */
318 /* TODO teensy via U30 PCA9543A bus 1 */
319 &i2c1 { /* i2c1 MIO 36-37 */
321 clock-frequency = <400000>;
323 /* Must be enabled via J242 */
324 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
325 compatible = "atmel,24c02";
329 i2c-mux@74 { /* u47 */
330 compatible = "nxp,pca9548";
331 #address-cells = <1>;
334 /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
335 dc_i2c: i2c@0 { /* DC_I2C */
336 #address-cells = <1>;
339 /* Use for storing information about SC board */
340 eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
341 compatible = "atmel,24c08";
344 si570_ref_clk: clock-generator@5d { /* u26 */
346 compatible = "silabs,si570";
347 reg = <0x5d>; /* FIXME addr */
348 temperature-stability = <50>;
349 factory-fout = <156250000>; /* FIXME every chip can be different */
350 clock-frequency = <33333333>;
351 clock-output-names = "REF_CLK"; /* FIXME */
353 /* Connection via Samtec U20D */
354 /* Use for storing information about X-PRC card */
355 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
356 compatible = "atmel,24c02";
360 /* Use for setting up certain features on X-PRC card */
361 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
362 compatible = "nxp,pca9534";
364 gpio-controller; /* IRQ not connected */
366 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
371 input; /* FIXME add meaning */
377 input; /* FIXME add meaning */
383 input; /* FIXME add meaning */
389 input; /* FIXME add meaning */
395 #address-cells = <1>;
398 si570_c0_lp4: clock-generator@55 { /* u10 */
400 compatible = "silabs,si570";
402 temperature-stability = <50>;
403 factory-fout = <30000000>;
404 clock-frequency = <30000000>;
405 clock-output-names = "C0_LP4_SI570_CLK";
409 #address-cells = <1>;
412 si570_c1_lp4: clock-generator@5d { /* u10 */
414 compatible = "silabs,si570";
415 reg = <0x5d>; /* FIXME addr */
416 temperature-stability = <50>;
417 factory-fout = <30000000>;
418 clock-frequency = <30000000>;
419 clock-output-names = "C1_LP4_SI570_CLK";
423 #address-cells = <1>;
426 si570_c2_lp4: clock-generator@55 { /* u10 */
428 compatible = "silabs,si570";
430 temperature-stability = <50>;
431 factory-fout = <30000000>;
432 clock-frequency = <30000000>;
433 clock-output-names = "C2_LP4_SI570_CLK";
437 #address-cells = <1>;
440 si570_c3_lp4: clock-generator@55 { /* u15 */
442 compatible = "silabs,si570";
444 temperature-stability = <50>;
445 factory-fout = <30000000>;
446 clock-frequency = <30000000>;
447 clock-output-names = "C3_LP4_SI570_CLK";
450 i2c@6 { /* HSDP_SI570 */
451 #address-cells = <1>;
454 si570_hsdp: clock-generator@5d { /* u19 */
456 compatible = "silabs,si570";
457 reg = <0x5d>; /* FIXME addr */
458 temperature-stability = <50>;
459 factory-fout = <156250000>;
460 clock-frequency = <156250000>;
461 clock-output-names = "HSDP_SI570";
469 xlnx,usb-polarity = <0>;
470 xlnx,usb-reset-mode = <0>;
476 /* dr_mode = "peripheral"; */
477 maximum-speed = "high-speed";
481 status = "disabled"; /* not at mem board */
482 xlnx,usb-polarity = <0>;
483 xlnx,usb-reset-mode = <0>;
487 /delete-property/ phy-names ;
488 /delete-property/ phys ;
489 maximum-speed = "high-speed";
490 snps,dis_u2_susphy_quirk ;
491 snps,dis_u3_susphy_quirk ;