1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx Versal a2197 RevA System Controller on MGT
5 * (C) Copyright 2019, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
11 #include "zynqmp.dtsi"
12 #include "zynqmp-clk-ccf.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
16 model = "Versal System Controller on a2197 MGT Char board RevA";
17 compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
18 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
32 bootargs = "earlycon";
33 stdout-path = "serial0:115200n8";
34 xlnx,eeprom = <&eeprom>;
38 device_type = "memory";
39 reg = <0x0 0x0 0x0 0x80000000>;
43 compatible = "iio-hwmon";
44 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
47 compatible = "iio-hwmon";
48 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
51 compatible = "iio-hwmon";
52 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
55 compatible = "iio-hwmon";
56 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
59 compatible = "iio-hwmon";
60 io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;
63 compatible = "iio-hwmon";
64 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
68 &sdhci0 { /* emmc MIO 13-23 16GB */
76 &uart0 { /* uart0 MIO38-39 */
81 &gem0 { /* eth MDIO 76/77 */
86 phy0: ethernet-phy@0 { /* marwell m88e1512 */
88 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
89 /* xlnx,phy-type = <PHY_TYPE_SGMII>; */
92 phys = <&lane0 PHY_TYPE_SGMII ... >
93 Note: lane0 sgmii/lane1 usb3 */
98 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
99 "", "", "", "", "", /* 5 - 9 */
100 "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
101 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
102 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
103 "", "", "", "", "", /* 25 - 29 */
104 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
105 "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
106 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
107 "", "", "", "", "", /* 45 - 49 */
108 "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
109 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
110 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
111 "", "", "", "", "", /* 65 - 69 */
112 "", "", "", "", "", /* 70 - 74 */
113 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
114 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
115 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
116 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
117 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
118 "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
119 "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
120 "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
121 "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
122 "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
123 "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
124 "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
125 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
126 "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
127 "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
128 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
129 "", "", "", "", "", /* 150 - 154 */
130 "", "", "", "", "", /* 155 - 159 */
131 "", "", "", "", "", /* 160 - 164 */
132 "", "", "", "", "", /* 165 - 169 */
133 "", "", "", ""; /* 170 - 174 */
136 &i2c0 { /* MIO 34-35 - can't stay here */
138 clock-frequency = <400000>;
139 scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;
140 sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
141 i2c-mux@74 { /* u94 */
142 compatible = "nxp,pca9548";
143 #address-cells = <1>;
146 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
148 #address-cells = <1>;
151 /* Use for storing information about SC board */
152 eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */
153 compatible = "atmel,24c32";
157 i2c@1 { /* CM_I2C_SCL - Samtec */
158 #address-cells = <1>;
162 i2c@2 { /* PMBUS - AFX_PMBUS */
163 #address-cells = <1>;
167 compatible = "ti,tps544b25";
170 tps544@10 { /* u73 */
171 compatible = "ti,tps544b25";
174 tps544@11 { /* u76 */
175 compatible = "ti,tps544b25";
178 tps544@12 { /* u77 */
179 compatible = "ti,tps544b25";
182 tps544@13 { /* u80 */
183 compatible = "ti,tps544b25";
186 tps544@14 { /* u81 */
187 compatible = "ti,tps544b25";
190 tps544@15 { /* u83 */
191 compatible = "ti,tps544b25";
194 tps544@16 { /* u63 */
195 compatible = "ti,tps544b25";
198 tps544@17 { /* u66 */
199 compatible = "ti,tps544b25";
202 tps544@18 { /* u67 */
203 compatible = "ti,tps544b25";
206 tps544@19 { /* u69 */
207 compatible = "ti,tps544b25";
210 tps544@1d { /* u88 */
211 compatible = "ti,tps544b25";
214 tps544@1e { /* u89 */
215 compatible = "ti,tps544b25";
218 tps544@1f { /* u87 */
219 compatible = "ti,tps544b25";
222 tps544@20 { /* u71 */
223 compatible = "ti,tps544b25";
226 u74: ina226@40 { /* u74 */
227 compatible = "ti,ina226";
228 #io-channel-cells = <1>;
229 label = "ina226-u74";
231 shunt-resistor = <1000>;
233 u75: ina226@41 { /* u75 */
234 compatible = "ti,ina226";
235 #io-channel-cells = <1>;
236 label = "ina226-u75";
238 shunt-resistor = <1000>;
240 u78: ina226@42 { /* u78 */
241 compatible = "ti,ina226";
242 #io-channel-cells = <1>;
243 label = "ina226-u78";
245 shunt-resistor = <5000>;
247 u79: ina226@43 { /* u79 */
248 compatible = "ti,ina226";
249 #io-channel-cells = <1>;
250 label = "ina226-u79";
252 shunt-resistor = <1000>;
254 u82: ina226@44 { /* u82 */
255 compatible = "ti,ina226";
256 #io-channel-cells = <1>;
257 label = "ina226-u82";
259 shunt-resistor = <1000>;
261 u84: ina226@45 { /* u84 */
262 compatible = "ti,ina226";
263 #io-channel-cells = <1>;
264 label = "ina226-u84";
266 shunt-resistor = <5000>;
268 tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */
269 compatible = "ti,tps53681", "ti,tps53679";
273 i2c@3 { /* fmc1 via JA2G */
274 #address-cells = <1>;
277 eeprom_fmc1: eeprom@50 { /* on FMC */
278 compatible = "atmel,24c04";
282 i2c@4 { /* fmc2 via JA3G */
283 #address-cells = <1>;
286 eeprom_fmc2: eeprom@50 { /* on FMC */
287 compatible = "atmel,24c04";
291 i2c@5 { /* fmc3 via JA4G */
292 #address-cells = <1>;
295 eeprom_fmc3: eeprom@50 { /* on FMC */
296 compatible = "atmel,24c04";
300 i2c@6 { /* ddr dimm */
301 #address-cells = <1>;
309 &usb0 { /* USB0 MIO52-63 */
311 xlnx,usb-polarity = <0>;
312 xlnx,usb-reset-mode = <0>;
317 dr_mode = "peripheral";
318 maximum-speed = "high-speed";