2 * dts file for Xilinx ZynqMP ep108 development board
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include "zynqmp.dtsi"
14 #include "zynqmp-ep108-clk.dtsi"
17 model = "ZynqMP EP108";
32 bootargs = "earlycon";
33 stdout-path = "serial0:115200n8";
37 device_type = "memory";
38 reg = <0x0 0x0 0x0 0x40000000>;
53 phy-mode = "rgmii-id";
66 clock-frequency = <400000>;
68 compatible = "atmel,24c64";
75 clock-frequency = <400000>;
77 compatible = "atmel,24c64";
87 partition@0 { /* for testing purpose */
88 label = "nand-fsbl-uboot";
89 reg = <0x0 0x0 0x400000>;
91 partition@1 { /* for testing purpose */
93 reg = <0x0 0x400000 0x1400000>;
95 partition@2 { /* for testing purpose */
96 label = "nand-device-tree";
97 reg = <0x0 0x1800000 0x400000>;
99 partition@3 { /* for testing purpose */
100 label = "nand-rootfs";
101 reg = <0x0 0x1C00000 0x1400000>;
103 partition@4 { /* for testing purpose */
104 label = "nand-bitstream";
105 reg = <0x0 0x3000000 0x400000>;
107 partition@5 { /* for testing purpose */
109 reg = <0x0 0x3400000 0xFCC00000>;
116 compatible = "m25p80";
117 #address-cells = <1>;
120 spi-tx-bus-width = <1>;
121 spi-rx-bus-width = <4>;
122 spi-max-frequency = <10000000>;
123 partition@qspi-fsbl-uboot { /* for testing purpose */
124 label = "qspi-fsbl-uboot";
125 reg = <0x0 0x100000>;
127 partition@qspi-linux { /* for testing purpose */
128 label = "qspi-linux";
129 reg = <0x100000 0x500000>;
131 partition@qspi-device-tree { /* for testing purpose */
132 label = "qspi-device-tree";
133 reg = <0x600000 0x20000>;
135 partition@qspi-rootfs { /* for testing purpose */
136 label = "qspi-rootfs";
137 reg = <0x620000 0x5E0000>;
145 /* SATA Phy OOB timing settings */
146 ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
147 ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
148 ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
149 ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
150 ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
151 ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
152 ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
153 ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
170 spi0_flash0: spi0_flash0@0 {
171 compatible = "m25p80";
172 #address-cells = <1>;
174 spi-max-frequency = <50000000>;
178 label = "spi0_flash0";
179 reg = <0x0 0x100000>;
187 spi1_flash0: spi1_flash0@0 {
188 compatible = "m25p80";
189 #address-cells = <1>;
191 spi-max-frequency = <50000000>;
195 label = "spi1_flash0";
196 reg = <0x0 0x100000>;
211 dr_mode = "peripheral";
212 maximum-speed = "high-speed";
222 maximum-speed = "high-speed";
230 xlnx,max-pclock-frequency = <200000>;
234 xlnx,axi-clock-freq = <200000000>;