arch/arm/dts/zynqmp-ep108.dts

   1 /*
   2  * dts file for Xilinx ZynqMP ep108 development board
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-ep108-clk.dtsi"
  15
  16 / {
  17         model = "ZynqMP EP108";
  18
  19         aliases {
  20                 mmc0 = &sdhci0;
  21                 mmc1 = &sdhci1;
  22                 serial0 = &uart0;
  23                 spi0 = &qspi;
  24                 spi1 = &spi0;
  25                 spi2 = &spi1;
  26         };
  27
  28         chosen {
  29                 stdout-path = "serial0:115200n8";
  30         };
  31
  32         memory {
  33                 device_type = "memory";
  34                 reg = <0x0 0x0 0x40000000>;
  35         };
  36 };
  37
  38 &can0 {
  39         status = "okay";
  40 };
  41
  42 &gem0 {
  43         status = "okay";
  44         phy-handle = <&phy0>;
  45         phy-mode = "rgmii-id";
  46         phy0: phy@0 {
  47                 reg = <0>;
  48                 max-speed = <100>;
  49         };
  50 };
  51
  52 &gpio {
  53         status = "okay";
  54 };
  55
  56 &i2c0 {
  57         status = "okay";
  58         clock-frequency = <400000>;
  59         eeprom@54 {
  60                 compatible = "at,24c64";
  61                 reg = <0x54>;
  62         };
  63 };
  64
  65 &i2c1 {
  66         status = "okay";
  67         clock-frequency = <400000>;
  68         eeprom@55 {
  69                 compatible = "at,24c64";
  70                 reg = <0x55>;
  71         };
  72 };
  73
  74 &qspi {
  75         status = "okay";
  76         flash@0 {
  77                 compatible = "n25q512a11";
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 reg = <0x0>;
  81                 spi-tx-bus-width = <1>;
  82                 spi-rx-bus-width = <4>;
  83                 spi-max-frequency = <10000000>;
  84                 partition@qspi-fsbl-uboot { /* for testing purpose */
  85                         label = "qspi-fsbl-uboot";
  86                         reg = <0x0 0x100000>;
  87                 };
  88                 partition@qspi-linux { /* for testing purpose */
  89                         label = "qspi-linux";
  90                         reg = <0x100000 0x500000>;
  91                 };
  92                 partition@qspi-device-tree { /* for testing purpose */
  93                         label = "qspi-device-tree";
  94                         reg = <0x600000 0x20000>;
  95                 };
  96                 partition@qspi-rootfs { /* for testing purpose */
  97                         label = "qspi-rootfs";
  98                         reg = <0x620000 0x5E0000>;
  99                 };
 100         };
 101 };
 102
 103 &sata {
 104         status = "okay";
 105         ceva,broken-gen2;
 106 };
 107
 108 &sdhci0 {
 109         status = "okay";
 110 };
 111
 112 &sdhci1 {
 113         status = "okay";
 114 };
 115
 116 &spi0 {
 117         status = "okay";
 118         num-cs = <1>;
 119         spi0_flash0: spi0_flash0@0 {
 120                 compatible = "m25p80";
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 spi-max-frequency = <50000000>;
 124                 reg = <0>;
 125
 126                 spi0_flash0@00000000 {
 127                         label = "spi0_flash0";
 128                         reg = <0x0 0x100000>;
 129                 };
 130         };
 131 };
 132
 133 &spi1 {
 134         status = "okay";
 135         num-cs = <1>;
 136         spi1_flash0: spi1_flash0@0 {
 137                 compatible = "m25p80";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 spi-max-frequency = <50000000>;
 141                 reg = <0>;
 142
 143                 spi1_flash0@00000000 {
 144                         label = "spi1_flash0";
 145                         reg = <0x0 0x100000>;
 146                 };
 147         };
 148 };
 149
 150 &uart0 {
 151         status = "okay";
 152 };
 153
 154 &usb0 {
 155         status = "okay";
 156         dr_mode = "peripheral";
 157         maximum-speed = "high-speed";
 158 };
 159
 160 &usb1 {
 161         status = "okay";
 162         dr_mode = "host";
 163         maximum-speed = "high-speed";
 164 };
 165
 166 &watchdog0 {
 167         status = "okay";
 168 };
 169
 170 &xlnx_dp {
 171         xlnx,max-pclock-frequency = <200000>;
 172 };
 173
 174 &xlnx_dpdma {
 175         xlnx,axi-clock-freq = <200000000>;
 176 };