2 * Xilinx ZC702 board DTS
4 * Copyright (C) 2011 - 2015 Xilinx
5 * Copyright (C) 2012 National Instruments Corp.
7 * SPDX-License-Identifier: GPL-2.0+
10 #include "zynq-7000.dtsi"
13 model = "Zynq ZC702 Development Board";
14 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
24 device_type = "memory";
25 reg = <0x0 0x40000000>;
29 bootargs = "earlyprintk";
30 stdout-path = "serial0:115200n8";
34 compatible = "gpio-keys";
40 gpios = <&gpio0 12 0>;
41 linux,code = <108>; /* down */
47 gpios = <&gpio0 14 0>;
48 linux,code = <103>; /* up */
55 compatible = "gpio-leds";
59 gpios = <&gpio0 10 0>;
60 linux,default-trigger = "heartbeat";
65 compatible = "usb-nop-xceiv";
72 compatible = "mmio-sram";
73 reg = <0xfffc0000 0x10000>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_can0_default>;
84 ps-clk-frequency = <33333333>;
89 phy-mode = "rgmii-id";
90 phy-handle = <ðernet_phy>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_gem0_default>;
94 ethernet_phy: ethernet-phy@7 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_gpio0_default>;
106 clock-frequency = <400000>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_i2c0_default>;
111 compatible = "nxp,pca9548";
112 #address-cells = <1>;
117 #address-cells = <1>;
120 si570: clock-generator@5d {
122 compatible = "silabs,si570";
123 temperature-stability = <50>;
125 factory-fout = <156250000>;
126 clock-frequency = <148500000>;
131 #address-cells = <1>;
135 compatible = "at,24c08";
141 #address-cells = <1>;
145 compatible = "ti,tca6416";
153 #address-cells = <1>;
157 compatible = "nxp,pcf8563";
163 #address-cells = <1>;
167 compatible = "ti,ucd9248";
171 compatible = "ti,ucd9248";
175 compatible = "ti,ucd9248";
183 pinctrl_can0_default: can0-default {
186 groups = "can0_9_grp";
190 groups = "can0_9_grp";
206 pinctrl_gem0_default: gem0-default {
208 function = "ethernet0";
209 groups = "ethernet0_0_grp";
213 groups = "ethernet0_0_grp";
219 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
225 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
232 groups = "mdio0_0_grp";
236 groups = "mdio0_0_grp";
243 pinctrl_gpio0_default: gpio0-default {
246 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
247 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
248 "gpio0_13_grp", "gpio0_14_grp";
252 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
253 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
254 "gpio0_13_grp", "gpio0_14_grp";
260 pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
265 pins = "MIO7", "MIO8";
270 pinctrl_i2c0_default: i2c0-default {
272 groups = "i2c0_10_grp";
277 groups = "i2c0_10_grp";
284 pinctrl_sdhci0_default: sdhci0-default {
286 groups = "sdio0_2_grp";
291 groups = "sdio0_2_grp";
298 groups = "gpio0_0_grp";
299 function = "sdio0_cd";
303 groups = "gpio0_0_grp";
311 groups = "gpio0_15_grp";
312 function = "sdio0_wp";
316 groups = "gpio0_15_grp";
324 pinctrl_uart1_default: uart1-default {
326 groups = "uart1_10_grp";
331 groups = "uart1_10_grp";
347 pinctrl_usb0_default: usb0-default {
349 groups = "usb0_0_grp";
354 groups = "usb0_0_grp";
360 pins = "MIO29", "MIO31", "MIO36";
365 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
366 "MIO35", "MIO37", "MIO38", "MIO39";
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_sdhci0_default>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_uart1_default>;
392 usb-phy = <&usb_phy0>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_usb0_default>;