arch/arm/dts/zynq-syzygy-hub.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * SYZYGY Hub DTS
   4  *
   5  *  Copyright (C) 2011 - 2015 Xilinx
   6  *  Copyright (C) 2017 Opal Kelly Inc.
   7  */
   8 /dts-v1/;
   9 /include/ "zynq-7000.dtsi"
  10
  11 / {
  12         model = "SYZYGY Hub";
  13         compatible = "opalkelly,syzygy-hub", "xlnx,zynq-7000";
  14
  15         aliases {
  16                 ethernet0 = &gem0;
  17                 serial0 = &uart0;
  18                 mmc0 = &sdhci0;
  19                 i2c0 = &i2c1;
  20         };
  21
  22         memory@0 {
  23                 device_type = "memory";
  24                 reg = <0x0 0x40000000>;
  25         };
  26
  27         chosen {
  28                 bootargs = "";
  29                 stdout-path = "serial0:115200n8";
  30                 xlnx,eeprom = &eeprom;
  31         };
  32
  33         usb_phy0: phy0 {
  34                 #phy-cells = <0>;
  35                 compatible = "usb-nop-xceiv";
  36                 reset-gpios = <&gpio0 47 1>;
  37         };
  38 };
  39
  40 &clkc {
  41         ps-clk-frequency = <50000000>;
  42 };
  43
  44 &gem0 {
  45         status = "okay";
  46         phy-mode = "rgmii-id";
  47         phy-handle = <&ethernet_phy>;
  48
  49         ethernet_phy: ethernet-phy@0 {
  50                 reg = <0>;
  51                 device_type = "ethernet-phy";
  52         };
  53 };
  54
  55 &i2c1 {
  56         status = "okay";
  57         eeprom: eeprom@57 {
  58                 compatible = "atmel,24c08"; /* not sure if this is correct */
  59                 reg = <0x57>;
  60         };
  61 };
  62
  63 &sdhci0 {
  64         u-boot,dm-pre-reloc;
  65         status = "okay";
  66 };
  67
  68 &uart0 {
  69         u-boot,dm-pre-reloc;
  70         status = "okay";
  71 };
  72
  73 &usb0 {
  74         status = "okay";
  75         dr_mode = "otg";
  76         usb-phy = <&usb_phy0>;
  77 };