1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Xilinx, Inc.
5 * Michal Simek <michal.simek@xilinx.com>
8 #include "zynq-7000.dtsi"
11 model = "Zynq DLC20 Rev1.0";
12 compatible = "xlnx,zynq-dlc20-rev1.0", "xlnx,zynq-dlc20",
24 device_type = "memory";
25 reg = <0x0 0x20000000>;
29 bootargs = "earlyprintk";
30 stdout-path = "serial0:115200n8";
33 usb_phy0: phy0@e0002000 {
34 compatible = "ulpi-phy";
36 reg = <0xe0002000 0x1000>;
43 ps-clk-frequency = <33333333>; /* U7 */
47 status = "okay"; /* MIO16-MIO27, MDIO MIO52/53 */
48 phy-mode = "rgmii-id";
49 phy-handle = <ðernet_phy>;
51 ethernet_phy: ethernet-phy@7 { /* rtl8211e - U25 */
57 status = "okay"; /* MIO14/15 */
58 clock-frequency = <400000>;
61 compatible = "atmel,24c08";
71 spi-tx-bus-width = <4>;
72 spi-rx-bus-width = <4>;
74 /* Rev1.0 W25Q128FWSIG, RevC N25Q128A */
75 compatible = "n25q128a11", "jedec,spi-nor";
77 spi-tx-bus-width = <1>;
78 spi-rx-bus-width = <4>;
79 spi-max-frequency = <50000000>;
85 status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */
92 status = "okay"; /* MIO8/9 */
96 status = "okay"; /* MIO28-MIO39 */
98 usb-phy = <&usb_phy0>;