1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx CSE NOR board DTS
5 * Copyright (C) 2018 Xilinx, Inc.
8 #include "zynq-7000.dtsi"
13 model = "Zynq CSE NOR Board";
14 compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
21 device_type = "memory";
22 reg = <0xFFFC0000 0x40000>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,dcc";
36 compatible = "simple-bus";
39 interrupt-parent = <&intc>;
42 intc: interrupt-controller@f8f01000 {
43 compatible = "arm,cortex-a9-gic";
44 #interrupt-cells = <3>;
46 reg = <0xF8F01000 0x1000>,
53 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
54 reg = <0xF8000000 0x1000>;
58 compatible = "xlnx,ps7-clkc";
60 clock-output-names = "armpll", "ddrpll",
62 "cpu_3or2x", "cpu_2x", "cpu_1x",
63 "ddr2x", "ddr3x", "dci",
64 "lqspi", "smc", "pcap", "gem0",
65 "gem1", "fclk0", "fclk1",
66 "fclk2", "fclk3", "can0",
67 "can1", "sdio0", "sdio1",
68 "uart0", "uart1", "spi0",
69 "spi1", "dma", "usb0_aper",
70 "usb1_aper", "gem0_aper",
71 "gem1_aper", "sdio0_aper",
72 "sdio1_aper", "spi0_aper",
73 "spi1_aper", "can0_aper",
74 "can1_aper", "i2c0_aper",
75 "i2c1_aper", "uart0_aper",
76 "uart1_aper", "gpio_aper",
77 "lqspi_aper", "smc_aper",
78 "swdt", "dbg_trc", "dbg_apb";