arch/arm/dts/zynq-cse-nand.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Xilinx CSE NAND board DTS
   4  *
   5  * Copyright (C) 2018 Xilinx, Inc.
   6  */
   7 /dts-v1/;
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         model = "Zynq CSE NAND Board";
  13         compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000";
  14
  15         aliases {
  16                 serial0 = &dcc;
  17         };
  18
  19         memory@0 {
  20                 device_type = "memory";
  21                 reg = <0x0 0x400000>;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26         };
  27
  28         dcc: dcc {
  29                 compatible = "arm,dcc";
  30                 status = "disabled";
  31                 u-boot,dm-pre-reloc;
  32         };
  33
  34         amba: amba {
  35                 u-boot,dm-pre-reloc;
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 ranges;
  40
  41                 smcc: memory-controller@e000e000 {
  42                         #address-cells = <1>;
  43                         #size-cells = <1>;
  44                         clock-names = "memclk", "apb_pclk";
  45                         clocks = <&clkc 11>, <&clkc 44>;
  46                         compatible = "arm,pl353-smc-r2p1", "arm,primecell";
  47                         ranges;
  48                         reg = <0xe000e000 0x1000>;
  49
  50                         nand0: flash@e1000000 {
  51                                 compatible = "arm,pl353-nand-r2p1";
  52                                 reg = <0xe1000000 0x1000000>;
  53                         };
  54                 };
  55
  56                 slcr: slcr@f8000000 {
  57                         u-boot,dm-pre-reloc;
  58                         #address-cells = <1>;
  59                         #size-cells = <1>;
  60                         compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
  61                         reg = <0xF8000000 0x1000>;
  62                         ranges;
  63                         clkc: clkc@100 {
  64                                 u-boot,dm-pre-reloc;
  65                                 #clock-cells = <1>;
  66                                 compatible = "xlnx,ps7-clkc";
  67                                 clock-output-names = "armpll", "ddrpll",
  68                                                 "iopll", "cpu_6or4x",
  69                                                 "cpu_3or2x", "cpu_2x", "cpu_1x",
  70                                                 "ddr2x", "ddr3x", "dci",
  71                                                 "lqspi", "smc", "pcap", "gem0",
  72                                                 "gem1", "fclk0", "fclk1",
  73                                                 "fclk2", "fclk3", "can0",
  74                                                 "can1", "sdio0", "sdio1",
  75                                                 "uart0", "uart1", "spi0",
  76                                                 "spi1", "dma", "usb0_aper",
  77                                                 "usb1_aper", "gem0_aper",
  78                                                 "gem1_aper", "sdio0_aper",
  79                                                 "sdio1_aper", "spi0_aper",
  80                                                 "spi1_aper", "can0_aper",
  81                                                 "can1_aper", "i2c0_aper",
  82                                                 "i2c1_aper", "uart0_aper",
  83                                                 "uart1_aper", "gpio_aper",
  84                                                 "lqspi_aper", "smc_aper",
  85                                                 "swdt", "dbg_trc", "dbg_apb";
  86                                 reg = <0x100 0x100>;
  87                         };
  88                 };
  89         };
  90 };
  91
  92 &dcc {
  93         status = "okay";
  94 };