1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx Zynq 7000 DTSI
4 * Describes the hardware common to all Zynq 7000-based boards.
6 * Copyright (C) 2011 - 2015 Xilinx
12 compatible = "xlnx,zynq-7000";
19 compatible = "arm,cortex-a9";
23 clock-latency = <1000>;
24 cpu0-supply = <®ulator_vccpint>;
33 compatible = "arm,cortex-a9";
40 fpga_full: fpga-full {
41 compatible = "fpga-region";
49 compatible = "arm,cortex-a9-pmu";
50 interrupts = <0 5 4>, <0 6 4>;
51 interrupt-parent = <&intc>;
52 reg = <0xf8891000 0x1000>,
56 regulator_vccpint: fixedregulator {
57 compatible = "regulator-fixed";
58 regulator-name = "VCCPINT";
59 regulator-min-microvolt = <1000000>;
60 regulator-max-microvolt = <1000000>;
67 compatible = "simple-bus";
70 interrupt-parent = <&intc>;
74 compatible = "xlnx,zynq-xadc-1.00.a";
75 reg = <0xf8007100 0x20>;
77 interrupt-parent = <&intc>;
82 compatible = "xlnx,zynq-can-1.0";
84 clocks = <&clkc 19>, <&clkc 36>;
85 clock-names = "can_clk", "pclk";
86 reg = <0xe0008000 0x1000>;
87 interrupts = <0 28 4>;
88 interrupt-parent = <&intc>;
89 tx-fifo-depth = <0x40>;
90 rx-fifo-depth = <0x40>;
94 compatible = "xlnx,zynq-can-1.0";
96 clocks = <&clkc 20>, <&clkc 37>;
97 clock-names = "can_clk", "pclk";
98 reg = <0xe0009000 0x1000>;
99 interrupts = <0 51 4>;
100 interrupt-parent = <&intc>;
101 tx-fifo-depth = <0x40>;
102 rx-fifo-depth = <0x40>;
105 gpio0: gpio@e000a000 {
106 compatible = "xlnx,zynq-gpio-1.0";
110 interrupt-controller;
111 #interrupt-cells = <2>;
112 interrupt-parent = <&intc>;
113 interrupts = <0 20 4>;
114 reg = <0xe000a000 0x1000>;
118 compatible = "cdns,i2c-r1p10";
121 interrupt-parent = <&intc>;
122 interrupts = <0 25 4>;
123 reg = <0xe0004000 0x1000>;
124 #address-cells = <1>;
129 compatible = "cdns,i2c-r1p10";
132 interrupt-parent = <&intc>;
133 interrupts = <0 48 4>;
134 reg = <0xe0005000 0x1000>;
135 #address-cells = <1>;
139 intc: interrupt-controller@f8f01000 {
140 compatible = "arm,cortex-a9-gic";
141 #interrupt-cells = <3>;
142 interrupt-controller;
143 reg = <0xF8F01000 0x1000>,
147 L2: cache-controller@f8f02000 {
148 compatible = "arm,pl310-cache";
149 reg = <0xF8F02000 0x1000>;
150 interrupts = <0 2 4>;
151 arm,data-latency = <3 2 2>;
152 arm,tag-latency = <2 2 2>;
157 mc: memory-controller@f8006000 {
158 compatible = "xlnx,zynq-ddrc-a05";
159 reg = <0xf8006000 0x1000>;
162 uart0: serial@e0000000 {
163 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
165 clocks = <&clkc 23>, <&clkc 40>;
166 clock-names = "uart_clk", "pclk";
167 reg = <0xE0000000 0x1000>;
168 interrupts = <0 27 4>;
171 uart1: serial@e0001000 {
172 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
174 clocks = <&clkc 24>, <&clkc 41>;
175 clock-names = "uart_clk", "pclk";
176 reg = <0xE0001000 0x1000>;
177 interrupts = <0 50 4>;
181 compatible = "xlnx,zynq-spi-r1p6";
182 reg = <0xe0006000 0x1000>;
184 interrupt-parent = <&intc>;
185 interrupts = <0 26 4>;
186 clocks = <&clkc 25>, <&clkc 34>;
187 clock-names = "ref_clk", "pclk";
188 #address-cells = <1>;
193 compatible = "xlnx,zynq-spi-r1p6";
194 reg = <0xe0007000 0x1000>;
196 interrupt-parent = <&intc>;
197 interrupts = <0 49 4>;
198 clocks = <&clkc 26>, <&clkc 35>;
199 clock-names = "ref_clk", "pclk";
200 #address-cells = <1>;
205 clock-names = "ref_clk", "pclk";
206 clocks = <&clkc 10>, <&clkc 43>;
207 compatible = "xlnx,zynq-qspi-1.0";
209 interrupt-parent = <&intc>;
210 interrupts = <0 19 4>;
211 reg = <0xe000d000 0x1000>;
212 #address-cells = <1>;
216 smcc: memory-controller@e000e000 {
217 #address-cells = <1>;
220 clock-names = "memclk", "apb_pclk";
221 clocks = <&clkc 11>, <&clkc 44>;
222 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
223 interrupt-parent = <&intc>;
224 interrupts = <0 18 4>;
226 reg = <0xe000e000 0x1000>;
227 nand0: flash@e1000000 {
229 compatible = "arm,pl353-nand-r2p1";
230 reg = <0xe1000000 0x1000000>;
231 #address-cells = <1>;
234 nor0: flash@e2000000 {
236 compatible = "cfi-flash";
237 reg = <0xe2000000 0x2000000>;
238 #address-cells = <1>;
243 gem0: ethernet@e000b000 {
244 compatible = "cdns,zynq-gem", "cdns,gem";
245 reg = <0xe000b000 0x1000>;
247 interrupts = <0 22 4>;
248 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
249 clock-names = "pclk", "hclk", "tx_clk";
250 #address-cells = <1>;
254 gem1: ethernet@e000c000 {
255 compatible = "cdns,zynq-gem", "cdns,gem";
256 reg = <0xe000c000 0x1000>;
258 interrupts = <0 45 4>;
259 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
260 clock-names = "pclk", "hclk", "tx_clk";
261 #address-cells = <1>;
265 sdhci0: mmc@e0100000 {
266 compatible = "arasan,sdhci-8.9a";
268 clock-names = "clk_xin", "clk_ahb";
269 clocks = <&clkc 21>, <&clkc 32>;
270 interrupt-parent = <&intc>;
271 interrupts = <0 24 4>;
272 reg = <0xe0100000 0x1000>;
275 sdhci1: mmc@e0101000 {
276 compatible = "arasan,sdhci-8.9a";
278 clock-names = "clk_xin", "clk_ahb";
279 clocks = <&clkc 22>, <&clkc 33>;
280 interrupt-parent = <&intc>;
281 interrupts = <0 47 4>;
282 reg = <0xe0101000 0x1000>;
285 slcr: slcr@f8000000 {
287 #address-cells = <1>;
289 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
290 reg = <0xF8000000 0x1000>;
295 compatible = "xlnx,ps7-clkc";
297 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
298 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
299 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
300 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
301 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
302 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
303 "gem1_aper", "sdio0_aper", "sdio1_aper",
304 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
305 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
306 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
307 "dbg_trc", "dbg_apb";
312 compatible = "xlnx,zynq-reset";
318 pinctrl0: pinctrl@700 {
319 compatible = "xlnx,pinctrl-zynq";
325 dmac_s: dmac@f8003000 {
326 compatible = "arm,pl330", "arm,primecell";
327 reg = <0xf8003000 0x1000>;
328 interrupt-parent = <&intc>;
329 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
330 "dma4", "dma5", "dma6", "dma7";
331 interrupts = <0 13 4>,
340 clock-names = "apb_pclk";
343 devcfg: devcfg@f8007000 {
344 compatible = "xlnx,zynq-devcfg-1.0";
345 interrupt-parent = <&intc>;
346 interrupts = <0 8 4>;
347 reg = <0xf8007000 0x100>;
348 clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
349 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
353 efuse: efuse@f800d000 {
354 compatible = "xlnx,zynq-efuse";
355 reg = <0xf800d000 0x20>;
358 global_timer: timer@f8f00200 {
359 compatible = "arm,cortex-a9-global-timer";
360 reg = <0xf8f00200 0x20>;
361 interrupts = <1 11 0x301>;
362 interrupt-parent = <&intc>;
366 ttc0: timer@f8001000 {
367 interrupt-parent = <&intc>;
368 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
369 compatible = "cdns,ttc";
371 reg = <0xF8001000 0x1000>;
374 ttc1: timer@f8002000 {
375 interrupt-parent = <&intc>;
376 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
377 compatible = "cdns,ttc";
379 reg = <0xF8002000 0x1000>;
382 scutimer: timer@f8f00600 {
383 interrupt-parent = <&intc>;
384 interrupts = <1 13 0x301>;
385 compatible = "arm,cortex-a9-twd-timer";
386 reg = <0xf8f00600 0x20>;
391 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
394 interrupt-parent = <&intc>;
395 interrupts = <0 21 4>;
396 reg = <0xe0002000 0x1000>;
401 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
404 interrupt-parent = <&intc>;
405 interrupts = <0 44 4>;
406 reg = <0xe0003000 0x1000>;
410 watchdog0: watchdog@f8005000 {
412 compatible = "cdns,wdt-r1p2";
413 interrupt-parent = <&intc>;
414 interrupts = <0 9 1>;
415 reg = <0xf8005000 0x1000>;