arch/arm/dts/zynq-7000.dtsi

   1 /*
   2  * Xilinx Zynq 7000 DTSI
   3  * Describes the hardware common to all Zynq 7000-based boards.
   4  *
   5  *  Copyright (C) 2011 - 2015 Xilinx
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "xlnx,zynq-7000";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         compatible = "arm,cortex-a9";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                         clocks = <&clkc 3>;
  23                         clock-latency = <1000>;
  24                         cpu0-supply = <&regulator_vccpint>;
  25                         operating-points = <
  26                                 /* kHz    uV */
  27                                 666667  1000000
  28                                 333334  1000000
  29                         >;
  30                 };
  31
  32                 cpu@1 {
  33                         compatible = "arm,cortex-a9";
  34                         device_type = "cpu";
  35                         reg = <1>;
  36                         clocks = <&clkc 3>;
  37                 };
  38         };
  39
  40         pmu {
  41                 compatible = "arm,cortex-a9-pmu";
  42                 interrupts = <0 5 4>, <0 6 4>;
  43                 interrupt-parent = <&intc>;
  44                 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
  45         };
  46
  47         regulator_vccpint: fixedregulator@0 {
  48                 compatible = "regulator-fixed";
  49                 regulator-name = "VCCPINT";
  50                 regulator-min-microvolt = <1000000>;
  51                 regulator-max-microvolt = <1000000>;
  52                 regulator-boot-on;
  53                 regulator-always-on;
  54         };
  55
  56         amba: amba {
  57                 u-boot,dm-pre-reloc;
  58                 compatible = "simple-bus";
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 interrupt-parent = <&intc>;
  62                 ranges;
  63
  64                 adc: adc@f8007100 {
  65                         compatible = "xlnx,zynq-xadc-1.00.a";
  66                         reg = <0xf8007100 0x20>;
  67                         interrupts = <0 7 4>;
  68                         interrupt-parent = <&intc>;
  69                         clocks = <&clkc 12>;
  70                 };
  71
  72                 can0: can@e0008000 {
  73                         compatible = "xlnx,zynq-can-1.0";
  74                         status = "disabled";
  75                         clocks = <&clkc 19>, <&clkc 36>;
  76                         clock-names = "can_clk", "pclk";
  77                         reg = <0xe0008000 0x1000>;
  78                         interrupts = <0 28 4>;
  79                         interrupt-parent = <&intc>;
  80                         tx-fifo-depth = <0x40>;
  81                         rx-fifo-depth = <0x40>;
  82                 };
  83
  84                 can1: can@e0009000 {
  85                         compatible = "xlnx,zynq-can-1.0";
  86                         status = "disabled";
  87                         clocks = <&clkc 20>, <&clkc 37>;
  88                         clock-names = "can_clk", "pclk";
  89                         reg = <0xe0009000 0x1000>;
  90                         interrupts = <0 51 4>;
  91                         interrupt-parent = <&intc>;
  92                         tx-fifo-depth = <0x40>;
  93                         rx-fifo-depth = <0x40>;
  94                 };
  95
  96                 gpio0: gpio@e000a000 {
  97                         compatible = "xlnx,zynq-gpio-1.0";
  98                         #gpio-cells = <2>;
  99                         clocks = <&clkc 42>;
 100                         gpio-controller;
 101                         interrupt-parent = <&intc>;
 102                         interrupts = <0 20 4>;
 103                         reg = <0xe000a000 0x1000>;
 104                 };
 105
 106                 i2c0: i2c@e0004000 {
 107                         compatible = "cdns,i2c-r1p10";
 108                         status = "disabled";
 109                         clocks = <&clkc 38>;
 110                         interrupt-parent = <&intc>;
 111                         interrupts = <0 25 4>;
 112                         reg = <0xe0004000 0x1000>;
 113                         #address-cells = <1>;
 114                         #size-cells = <0>;
 115                 };
 116
 117                 i2c1: i2c@e0005000 {
 118                         compatible = "cdns,i2c-r1p10";
 119                         status = "disabled";
 120                         clocks = <&clkc 39>;
 121                         interrupt-parent = <&intc>;
 122                         interrupts = <0 48 4>;
 123                         reg = <0xe0005000 0x1000>;
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                 };
 127
 128                 intc: interrupt-controller@f8f01000 {
 129                         compatible = "arm,cortex-a9-gic";
 130                         #interrupt-cells = <3>;
 131                         interrupt-controller;
 132                         reg = <0xF8F01000 0x1000>,
 133                               <0xF8F00100 0x100>;
 134                 };
 135
 136                 L2: cache-controller@f8f02000 {
 137                         compatible = "arm,pl310-cache";
 138                         reg = <0xF8F02000 0x1000>;
 139                         interrupts = <0 2 4>;
 140                         arm,data-latency = <3 2 2>;
 141                         arm,tag-latency = <2 2 2>;
 142                         cache-unified;
 143                         cache-level = <2>;
 144                 };
 145
 146                 mc: memory-controller@f8006000 {
 147                         compatible = "xlnx,zynq-ddrc-a05";
 148                         reg = <0xf8006000 0x1000>;
 149                 };
 150
 151                 uart0: serial@e0000000 {
 152                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 153                         status = "disabled";
 154                         clocks = <&clkc 23>, <&clkc 40>;
 155                         clock-names = "uart_clk", "pclk";
 156                         reg = <0xE0000000 0x1000>;
 157                         interrupts = <0 27 4>;
 158                 };
 159
 160                 uart1: serial@e0001000 {
 161                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 162                         status = "disabled";
 163                         clocks = <&clkc 24>, <&clkc 41>;
 164                         clock-names = "uart_clk", "pclk";
 165                         reg = <0xE0001000 0x1000>;
 166                         interrupts = <0 50 4>;
 167                 };
 168
 169                 spi0: spi@e0006000 {
 170                         compatible = "xlnx,zynq-spi-r1p6";
 171                         reg = <0xe0006000 0x1000>;
 172                         status = "disabled";
 173                         interrupt-parent = <&intc>;
 174                         interrupts = <0 26 4>;
 175                         clocks = <&clkc 25>, <&clkc 34>;
 176                         clock-names = "ref_clk", "pclk";
 177                         spi-max-frequency = <166666700>;
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                 };
 181
 182                 spi1: spi@e0007000 {
 183                         compatible = "xlnx,zynq-spi-r1p6";
 184                         reg = <0xe0007000 0x1000>;
 185                         status = "disabled";
 186                         interrupt-parent = <&intc>;
 187                         interrupts = <0 49 4>;
 188                         clocks = <&clkc 26>, <&clkc 35>;
 189                         clock-names = "ref_clk", "pclk";
 190                         spi-max-frequency = <166666700>;
 191                         #address-cells = <1>;
 192                         #size-cells = <0>;
 193                 };
 194
 195                 qspi: spi@e000d000 {
 196                         clock-names = "ref_clk", "pclk";
 197                         clocks = <&clkc 10>, <&clkc 43>;
 198                         compatible = "xlnx,zynq-qspi-1.0";
 199                         status = "disabled";
 200                         interrupt-parent = <&intc>;
 201                         interrupts = <0 19 4>;
 202                         reg = <0xe000d000 0x1000>;
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                 };
 206
 207                 gem0: ethernet@e000b000 {
 208                         compatible = "cdns,zynq-gem", "cdns,gem";
 209                         reg = <0xe000b000 0x1000>;
 210                         status = "disabled";
 211                         interrupts = <0 22 4>;
 212                         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
 213                         clock-names = "pclk", "hclk", "tx_clk";
 214                         #address-cells = <1>;
 215                         #size-cells = <0>;
 216                 };
 217
 218                 gem1: ethernet@e000c000 {
 219                         compatible = "cdns,zynq-gem", "cdns,gem";
 220                         reg = <0xe000c000 0x1000>;
 221                         status = "disabled";
 222                         interrupts = <0 45 4>;
 223                         clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
 224                         clock-names = "pclk", "hclk", "tx_clk";
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                 };
 228
 229                 sdhci0: sdhci@e0100000 {
 230                         compatible = "arasan,sdhci-8.9a";
 231                         status = "disabled";
 232                         clock-names = "clk_xin", "clk_ahb";
 233                         clocks = <&clkc 21>, <&clkc 32>;
 234                         interrupt-parent = <&intc>;
 235                         interrupts = <0 24 4>;
 236                         reg = <0xe0100000 0x1000>;
 237                 };
 238
 239                 sdhci1: sdhci@e0101000 {
 240                         compatible = "arasan,sdhci-8.9a";
 241                         status = "disabled";
 242                         clock-names = "clk_xin", "clk_ahb";
 243                         clocks = <&clkc 22>, <&clkc 33>;
 244                         interrupt-parent = <&intc>;
 245                         interrupts = <0 47 4>;
 246                         reg = <0xe0101000 0x1000>;
 247                 };
 248
 249                 slcr: slcr@f8000000 {
 250                         #address-cells = <1>;
 251                         #size-cells = <1>;
 252                         compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
 253                         reg = <0xF8000000 0x1000>;
 254                         ranges;
 255                         clkc: clkc@100 {
 256                                 #clock-cells = <1>;
 257                                 compatible = "xlnx,ps7-clkc";
 258                                 fclk-enable = <0>;
 259                                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
 260                                                 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
 261                                                 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
 262                                                 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
 263                                                 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
 264                                                 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
 265                                                 "gem1_aper", "sdio0_aper", "sdio1_aper",
 266                                                 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
 267                                                 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
 268                                                 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
 269                                                 "dbg_trc", "dbg_apb";
 270                                 reg = <0x100 0x100>;
 271                         };
 272
 273                         pinctrl0: pinctrl@700 {
 274                                 compatible = "xlnx,pinctrl-zynq";
 275                                 reg = <0x700 0x200>;
 276                                 syscon = <&slcr>;
 277                         };
 278                 };
 279
 280                 dmac_s: dmac@f8003000 {
 281                         compatible = "arm,pl330", "arm,primecell";
 282                         reg = <0xf8003000 0x1000>;
 283                         interrupt-parent = <&intc>;
 284                         interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
 285                                 "dma4", "dma5", "dma6", "dma7";
 286                         interrupts = <0 13 4>,
 287                                      <0 14 4>, <0 15 4>,
 288                                      <0 16 4>, <0 17 4>,
 289                                      <0 40 4>, <0 41 4>,
 290                                      <0 42 4>, <0 43 4>;
 291                         #dma-cells = <1>;
 292                         #dma-channels = <8>;
 293                         #dma-requests = <4>;
 294                         clocks = <&clkc 27>;
 295                         clock-names = "apb_pclk";
 296                 };
 297
 298                 devcfg: devcfg@f8007000 {
 299                         compatible = "xlnx,zynq-devcfg-1.0";
 300                         reg = <0xf8007000 0x100>;
 301                 };
 302
 303                 global_timer: timer@f8f00200 {
 304                         compatible = "arm,cortex-a9-global-timer";
 305                         reg = <0xf8f00200 0x20>;
 306                         interrupts = <1 11 0x301>;
 307                         interrupt-parent = <&intc>;
 308                         clocks = <&clkc 4>;
 309                 };
 310
 311                 ttc0: timer@f8001000 {
 312                         interrupt-parent = <&intc>;
 313                         interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
 314                         compatible = "cdns,ttc";
 315                         clocks = <&clkc 6>;
 316                         reg = <0xF8001000 0x1000>;
 317                 };
 318
 319                 ttc1: timer@f8002000 {
 320                         interrupt-parent = <&intc>;
 321                         interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
 322                         compatible = "cdns,ttc";
 323                         clocks = <&clkc 6>;
 324                         reg = <0xF8002000 0x1000>;
 325                 };
 326
 327                 scutimer: timer@f8f00600 {
 328                         interrupt-parent = <&intc>;
 329                         interrupts = <1 13 0x301>;
 330                         compatible = "arm,cortex-a9-twd-timer";
 331                         reg = <0xf8f00600 0x20>;
 332                         clocks = <&clkc 4>;
 333                 };
 334
 335                 usb0: usb@e0002000 {
 336                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 337                         status = "disabled";
 338                         clocks = <&clkc 28>;
 339                         interrupt-parent = <&intc>;
 340                         interrupts = <0 21 4>;
 341                         reg = <0xe0002000 0x1000>;
 342                         phy_type = "ulpi";
 343                 };
 344
 345                 usb1: usb@e0003000 {
 346                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 347                         status = "disabled";
 348                         clocks = <&clkc 29>;
 349                         interrupt-parent = <&intc>;
 350                         interrupts = <0 44 4>;
 351                         reg = <0xe0003000 0x1000>;
 352                         phy_type = "ulpi";
 353                 };
 354
 355                 watchdog0: watchdog@f8005000 {
 356                         clocks = <&clkc 45>;
 357                         compatible = "cdns,wdt-r1p2";
 358                         interrupt-parent = <&intc>;
 359                         interrupts = <0 9 1>;
 360                         reg = <0xf8005000 0x1000>;
 361                         timeout-sec = <10>;
 362                 };
 363         };
 364 };