1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx Zynq 7000 DTSI
4 * Describes the hardware common to all Zynq 7000-based boards.
6 * Copyright (C) 2011 - 2015 Xilinx
12 compatible = "xlnx,zynq-7000";
19 compatible = "arm,cortex-a9";
23 clock-latency = <1000>;
24 cpu0-supply = <®ulator_vccpint>;
33 compatible = "arm,cortex-a9";
40 fpga_full: fpga-full {
41 compatible = "fpga-region";
49 compatible = "arm,cortex-a9-pmu";
50 interrupts = <0 5 4>, <0 6 4>;
51 interrupt-parent = <&intc>;
52 reg = <0xf8891000 0x1000>,
56 regulator_vccpint: fixedregulator {
57 compatible = "regulator-fixed";
58 regulator-name = "VCCPINT";
59 regulator-min-microvolt = <1000000>;
60 regulator-max-microvolt = <1000000>;
66 compatible = "arm,coresight-static-replicator";
67 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
68 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
74 /* replicator output ports */
77 replicator_out_port0: endpoint {
78 remote-endpoint = <&tpiu_in_port>;
83 replicator_out_port1: endpoint {
84 remote-endpoint = <&etb_in_port>;
89 /* replicator input port */
91 replicator_in_port0: endpoint {
92 remote-endpoint = <&funnel_out_port>;
100 compatible = "simple-bus";
101 #address-cells = <1>;
103 interrupt-parent = <&intc>;
107 compatible = "xlnx,zynq-xadc-1.00.a";
108 reg = <0xf8007100 0x20>;
109 interrupts = <0 7 4>;
110 interrupt-parent = <&intc>;
115 compatible = "xlnx,zynq-can-1.0";
117 clocks = <&clkc 19>, <&clkc 36>;
118 clock-names = "can_clk", "pclk";
119 reg = <0xe0008000 0x1000>;
120 interrupts = <0 28 4>;
121 interrupt-parent = <&intc>;
122 tx-fifo-depth = <0x40>;
123 rx-fifo-depth = <0x40>;
127 compatible = "xlnx,zynq-can-1.0";
129 clocks = <&clkc 20>, <&clkc 37>;
130 clock-names = "can_clk", "pclk";
131 reg = <0xe0009000 0x1000>;
132 interrupts = <0 51 4>;
133 interrupt-parent = <&intc>;
134 tx-fifo-depth = <0x40>;
135 rx-fifo-depth = <0x40>;
138 gpio0: gpio@e000a000 {
139 compatible = "xlnx,zynq-gpio-1.0";
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 interrupt-parent = <&intc>;
146 interrupts = <0 20 4>;
147 reg = <0xe000a000 0x1000>;
151 compatible = "cdns,i2c-r1p10";
154 interrupt-parent = <&intc>;
155 interrupts = <0 25 4>;
156 reg = <0xe0004000 0x1000>;
157 #address-cells = <1>;
162 compatible = "cdns,i2c-r1p10";
165 interrupt-parent = <&intc>;
166 interrupts = <0 48 4>;
167 reg = <0xe0005000 0x1000>;
168 #address-cells = <1>;
172 intc: interrupt-controller@f8f01000 {
173 compatible = "arm,cortex-a9-gic";
174 #interrupt-cells = <3>;
175 interrupt-controller;
176 reg = <0xF8F01000 0x1000>,
180 L2: cache-controller@f8f02000 {
181 compatible = "arm,pl310-cache";
182 reg = <0xF8F02000 0x1000>;
183 interrupts = <0 2 4>;
184 arm,data-latency = <3 2 2>;
185 arm,tag-latency = <2 2 2>;
190 mc: memory-controller@f8006000 {
191 compatible = "xlnx,zynq-ddrc-a05";
192 reg = <0xf8006000 0x1000>;
195 uart0: serial@e0000000 {
196 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
198 clocks = <&clkc 23>, <&clkc 40>;
199 clock-names = "uart_clk", "pclk";
200 reg = <0xE0000000 0x1000>;
201 interrupts = <0 27 4>;
204 uart1: serial@e0001000 {
205 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
207 clocks = <&clkc 24>, <&clkc 41>;
208 clock-names = "uart_clk", "pclk";
209 reg = <0xE0001000 0x1000>;
210 interrupts = <0 50 4>;
214 compatible = "xlnx,zynq-spi-r1p6";
215 reg = <0xe0006000 0x1000>;
217 interrupt-parent = <&intc>;
218 interrupts = <0 26 4>;
219 clocks = <&clkc 25>, <&clkc 34>;
220 clock-names = "ref_clk", "pclk";
221 #address-cells = <1>;
226 compatible = "xlnx,zynq-spi-r1p6";
227 reg = <0xe0007000 0x1000>;
229 interrupt-parent = <&intc>;
230 interrupts = <0 49 4>;
231 clocks = <&clkc 26>, <&clkc 35>;
232 clock-names = "ref_clk", "pclk";
233 #address-cells = <1>;
238 clock-names = "ref_clk", "pclk";
239 clocks = <&clkc 10>, <&clkc 43>;
240 compatible = "xlnx,zynq-qspi-1.0";
242 interrupt-parent = <&intc>;
243 interrupts = <0 19 4>;
244 reg = <0xe000d000 0x1000>;
245 #address-cells = <1>;
249 smcc: memory-controller@e000e000 {
250 #address-cells = <1>;
253 clock-names = "memclk", "apb_pclk";
254 clocks = <&clkc 11>, <&clkc 44>;
255 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
256 interrupt-parent = <&intc>;
257 interrupts = <0 18 4>;
259 reg = <0xe000e000 0x1000>;
260 nand0: flash@e1000000 {
262 compatible = "arm,pl353-nand-r2p1";
263 reg = <0xe1000000 0x1000000>;
264 #address-cells = <1>;
267 nor0: flash@e2000000 {
269 compatible = "cfi-flash";
270 reg = <0xe2000000 0x2000000>;
271 #address-cells = <1>;
276 gem0: ethernet@e000b000 {
277 compatible = "cdns,zynq-gem", "cdns,gem";
278 reg = <0xe000b000 0x1000>;
280 interrupts = <0 22 4>;
281 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
282 clock-names = "pclk", "hclk", "tx_clk";
283 #address-cells = <1>;
287 gem1: ethernet@e000c000 {
288 compatible = "cdns,zynq-gem", "cdns,gem";
289 reg = <0xe000c000 0x1000>;
291 interrupts = <0 45 4>;
292 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
293 clock-names = "pclk", "hclk", "tx_clk";
294 #address-cells = <1>;
298 sdhci0: mmc@e0100000 {
299 compatible = "arasan,sdhci-8.9a";
301 clock-names = "clk_xin", "clk_ahb";
302 clocks = <&clkc 21>, <&clkc 32>;
303 interrupt-parent = <&intc>;
304 interrupts = <0 24 4>;
305 reg = <0xe0100000 0x1000>;
308 sdhci1: mmc@e0101000 {
309 compatible = "arasan,sdhci-8.9a";
311 clock-names = "clk_xin", "clk_ahb";
312 clocks = <&clkc 22>, <&clkc 33>;
313 interrupt-parent = <&intc>;
314 interrupts = <0 47 4>;
315 reg = <0xe0101000 0x1000>;
318 slcr: slcr@f8000000 {
320 #address-cells = <1>;
322 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
323 reg = <0xF8000000 0x1000>;
328 compatible = "xlnx,ps7-clkc";
330 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
331 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
332 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
333 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
334 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
335 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
336 "gem1_aper", "sdio0_aper", "sdio1_aper",
337 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
338 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
339 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
340 "dbg_trc", "dbg_apb";
345 compatible = "xlnx,zynq-reset";
351 pinctrl0: pinctrl@700 {
352 compatible = "xlnx,pinctrl-zynq";
358 dmac_s: dmac@f8003000 {
359 compatible = "arm,pl330", "arm,primecell";
360 reg = <0xf8003000 0x1000>;
361 interrupt-parent = <&intc>;
362 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
363 "dma4", "dma5", "dma6", "dma7";
364 interrupts = <0 13 4>,
373 clock-names = "apb_pclk";
376 devcfg: devcfg@f8007000 {
377 compatible = "xlnx,zynq-devcfg-1.0";
378 interrupt-parent = <&intc>;
379 interrupts = <0 8 4>;
380 reg = <0xf8007000 0x100>;
381 clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
382 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
386 efuse: efuse@f800d000 {
387 compatible = "xlnx,zynq-efuse";
388 reg = <0xf800d000 0x20>;
391 global_timer: timer@f8f00200 {
392 compatible = "arm,cortex-a9-global-timer";
393 reg = <0xf8f00200 0x20>;
394 interrupts = <1 11 0x301>;
395 interrupt-parent = <&intc>;
399 ttc0: timer@f8001000 {
400 interrupt-parent = <&intc>;
401 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
402 compatible = "cdns,ttc";
404 reg = <0xF8001000 0x1000>;
407 ttc1: timer@f8002000 {
408 interrupt-parent = <&intc>;
409 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
410 compatible = "cdns,ttc";
412 reg = <0xF8002000 0x1000>;
415 scutimer: timer@f8f00600 {
416 interrupt-parent = <&intc>;
417 interrupts = <1 13 0x301>;
418 compatible = "arm,cortex-a9-twd-timer";
419 reg = <0xf8f00600 0x20>;
424 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
427 interrupt-parent = <&intc>;
428 interrupts = <0 21 4>;
429 reg = <0xe0002000 0x1000>;
434 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
437 interrupt-parent = <&intc>;
438 interrupts = <0 44 4>;
439 reg = <0xe0003000 0x1000>;
443 watchdog0: watchdog@f8005000 {
445 compatible = "cdns,wdt-r1p2";
446 interrupt-parent = <&intc>;
447 interrupts = <0 9 1>;
448 reg = <0xf8005000 0x1000>;
453 compatible = "arm,coresight-etb10", "arm,primecell";
454 reg = <0xf8801000 0x1000>;
455 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
456 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
459 etb_in_port: endpoint {
460 remote-endpoint = <&replicator_out_port1>;
467 compatible = "arm,coresight-tpiu", "arm,primecell";
468 reg = <0xf8803000 0x1000>;
469 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
470 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
473 tpiu_in_port: endpoint {
474 remote-endpoint = <&replicator_out_port0>;
481 compatible = "arm,coresight-static-funnel", "arm,primecell";
482 reg = <0xf8804000 0x1000>;
483 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
484 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
486 /* funnel output ports */
489 funnel_out_port: endpoint {
491 <&replicator_in_port0>;
497 #address-cells = <1>;
500 /* funnel input ports */
503 funnel0_in_port0: endpoint {
504 remote-endpoint = <&ptm0_out_port>;
510 funnel0_in_port1: endpoint {
511 remote-endpoint = <&ptm1_out_port>;
517 funnel0_in_port2: endpoint {
520 /* The other input ports are not connect to anything */
525 compatible = "arm,coresight-etm3x", "arm,primecell";
526 reg = <0xf889c000 0x1000>;
527 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
528 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
532 ptm0_out_port: endpoint {
533 remote-endpoint = <&funnel0_in_port0>;
540 compatible = "arm,coresight-etm3x", "arm,primecell";
541 reg = <0xf889d000 0x1000>;
542 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
543 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
547 ptm1_out_port: endpoint {
548 remote-endpoint = <&funnel0_in_port1>;