arch/arm/dts/vf610-pcm052.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * (C) Copyright 2018
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
   5  *
   6  */
   7
   8 /dts-v1/;
   9 #include "vf.dtsi"
  10 #include "vf610-pinfunc.h"
  11
  12 / {
  13         chosen {
  14                 stdout-path = &uart1;
  15         };
  16
  17         aliases {
  18                 spi0 = &qspi0;
  19                 mmc0 = &esdhc1;
  20         };
  21 };
  22
  23 &esdhc1 {
  24         pinctrl-names = "default";
  25         pinctrl-0 = <&pinctrl_esdhc1>;
  26         bus-width = <4>;
  27         cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
  28         status = "okay";
  29 };
  30
  31 &fec0 {
  32         pinctrl-names = "default";
  33         pinctrl-0 = <&pinctrl_eth>;
  34
  35         phy-mode = "rmii";
  36         status = "okay";
  37 };
  38
  39 &fec1 {
  40         pinctrl-names = "default";
  41         pinctrl-0 = <&pinctrl_eth1>;
  42
  43         phy-mode = "rmii";
  44         status = "okay";
  45 };
  46
  47 &i2c2 {
  48         pinctrl-names = "default";
  49         pinctrl-0 = <&pinctrl_i2c2>;
  50         status = "okay";
  51
  52         eeprom: eeprom@50 {
  53                 compatible = "atmel,24c256";
  54                 reg = <0x50>;
  55                 pagesize = <64>;
  56                 u-boot,i2c-offset-len = <2>;
  57         };
  58
  59         m41t62: rtc@68 {
  60                 compatible = "st,m41t62";
  61                 reg = <0x68>;
  62         };
  63 };
  64
  65 &iomuxc {
  66         pinctrl-names = "default";
  67         pinctrl-0 = <&pinctrl_ddr>;
  68
  69         pinctrl_ddr: ddrgrp {
  70                 fsl,pins = <
  71                         VF610_PAD_DDR_A15__DDR_A_15             0x1c0
  72                         VF610_PAD_DDR_A14__DDR_A_14             0x1c0
  73                         VF610_PAD_DDR_A13__DDR_A_13             0x1c0
  74                         VF610_PAD_DDR_A12__DDR_A_12             0x1c0
  75                         VF610_PAD_DDR_A11__DDR_A_11             0x1c0
  76                         VF610_PAD_DDR_A10__DDR_A_10             0x1c0
  77                         VF610_PAD_DDR_A9__DDR_A_9               0x1c0
  78                         VF610_PAD_DDR_A8__DDR_A_8               0x1c0
  79                         VF610_PAD_DDR_A7__DDR_A_7               0x1c0
  80                         VF610_PAD_DDR_A6__DDR_A_6               0x1c0
  81                         VF610_PAD_DDR_A5__DDR_A_5               0x1c0
  82                         VF610_PAD_DDR_A4__DDR_A_4               0x1c0
  83                         VF610_PAD_DDR_A3__DDR_A_3               0x1c0
  84                         VF610_PAD_DDR_A2__DDR_A_2               0x1c0
  85                         VF610_PAD_DDR_A1__DDR_A_1               0x1c0
  86                         VF610_PAD_DDR_A0__DDR_A_0               0x1c0
  87                         VF610_PAD_DDR_BA2__DDR_BA_2             0x1c0
  88                         VF610_PAD_DDR_BA1__DDR_BA_1             0x1c0
  89                         VF610_PAD_DDR_BA0__DDR_BA_0             0x1c0
  90                         VF610_PAD_DDR_CAS__DDR_CAS_B            0x1c0
  91                         VF610_PAD_DDR_CKE__DDR_CKE_0            0x1c0
  92                         VF610_PAD_DDR_CLK__DDR_CLK_0            0x101c0
  93                         VF610_PAD_DDR_CS__DDR_CS_B_0            0x1c0
  94                         VF610_PAD_DDR_D15__DDR_D_15             0x1c0
  95                         VF610_PAD_DDR_D14__DDR_D_14             0x1c0
  96                         VF610_PAD_DDR_D13__DDR_D_13             0x1c0
  97                         VF610_PAD_DDR_D12__DDR_D_12             0x1c0
  98                         VF610_PAD_DDR_D11__DDR_D_11             0x1c0
  99                         VF610_PAD_DDR_D10__DDR_D_10             0x1c0
 100                         VF610_PAD_DDR_D9__DDR_D_9               0x1c0
 101                         VF610_PAD_DDR_D8__DDR_D_8               0x1c0
 102                         VF610_PAD_DDR_D7__DDR_D_7               0x1c0
 103                         VF610_PAD_DDR_D6__DDR_D_6               0x1c0
 104                         VF610_PAD_DDR_D5__DDR_D_5               0x1c0
 105                         VF610_PAD_DDR_D4__DDR_D_4               0x1c0
 106                         VF610_PAD_DDR_D3__DDR_D_3               0x1c0
 107                         VF610_PAD_DDR_D2__DDR_D_2               0x1c0
 108                         VF610_PAD_DDR_D1__DDR_D_1               0x1c0
 109                         VF610_PAD_DDR_D0__DDR_D_0               0x1c0
 110                         VF610_PAD_DDR_DQM1__DDR_DQM_1           0x1c0
 111                         VF610_PAD_DDR_DQM0__DDR_DQM_0           0x1c0
 112                         VF610_PAD_DDR_DQS1__DDR_DQS_1           0x101c0
 113                         VF610_PAD_DDR_DQS0__DDR_DQS_0           0x101c0
 114                         VF610_PAD_DDR_RAS__DDR_RAS_B            0x1c0
 115                         VF610_PAD_DDR_WE__DDR_WE_B              0x1c0
 116                         VF610_PAD_DDR_ODT1__DDR_ODT_0           0x1c0
 117                         VF610_PAD_DDR_ODT0__DDR_ODT_1           0x1c0
 118                         VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1    0x1c0
 119                         VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2    0x1c0
 120                         VF610_PAD_DDR_RESETB                    0x1006c
 121                 >;
 122         };
 123
 124         pinctrl_esdhc1: esdhc1grp {
 125                 fsl,pins = <
 126                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 127                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 128                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 129                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 130                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 131                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 132                         VF610_PAD_PTB28__GPIO_98                0x219d
 133                 >;
 134         };
 135
 136         pinctrl_eth: ethgrp {
 137                 fsl,pins = <
 138                         VF610_PAD_PTA6__RMII_CLKIN              0x30dd
 139                         VF610_PAD_PTC0__ENET_RMII0_MDC          0x30de
 140                         VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df
 141                         VF610_PAD_PTC2__ENET_RMII0_CRS          0x30dd
 142                         VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd
 143                         VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd
 144                         VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd
 145                         VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de
 146                         VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de
 147                         VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de
 148                 >;
 149         };
 150
 151         pinctrl_eth1: eth1grp {
 152                 fsl,pins = <
 153                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30de
 154                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30df
 155                         VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd
 156                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30dd
 157                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30dd
 158                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30dd
 159                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30de
 160                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30de
 161                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30de
 162                 >;
 163         };
 164
 165         pinctrl_i2c2: i2c2grp {
 166                 fsl,pins = <
 167                         VF610_PAD_PTA22__I2C2_SCL               0x34df
 168                         VF610_PAD_PTA23__I2C2_SDA               0x34df
 169                 >;
 170         };
 171
 172         pinctrl_nfc: nfcgrp {
 173                 fsl,pins = <
 174                         VF610_PAD_PTD31__NF_IO15                0x28df
 175                         VF610_PAD_PTD30__NF_IO14                0x28df
 176                         VF610_PAD_PTD29__NF_IO13                0x28df
 177                         VF610_PAD_PTD28__NF_IO12                0x28df
 178                         VF610_PAD_PTD27__NF_IO11                0x28df
 179                         VF610_PAD_PTD26__NF_IO10                0x28df
 180                         VF610_PAD_PTD25__NF_IO9         0x28df
 181                         VF610_PAD_PTD24__NF_IO8         0x28df
 182                         VF610_PAD_PTD23__NF_IO7         0x28df
 183                         VF610_PAD_PTD22__NF_IO6         0x28df
 184                         VF610_PAD_PTD21__NF_IO5         0x28df
 185                         VF610_PAD_PTD20__NF_IO4         0x28df
 186                         VF610_PAD_PTD19__NF_IO3         0x28df
 187                         VF610_PAD_PTD18__NF_IO2         0x28df
 188                         VF610_PAD_PTD17__NF_IO1         0x28df
 189                         VF610_PAD_PTD16__NF_IO0         0x28df
 190                         VF610_PAD_PTB24__NF_WE_B                0x28c2
 191                         VF610_PAD_PTB25__NF_CE0_B               0x28c2
 192                         VF610_PAD_PTB27__NF_RE_B                0x28c2
 193                         VF610_PAD_PTC26__NF_RB_B                0x283d
 194                         VF610_PAD_PTC27__NF_ALE         0x28c2
 195                         VF610_PAD_PTC28__NF_CLE         0x28c2
 196                 >;
 197         };
 198
 199         pinctrl_qspi0: qspi0grp {
 200                 fsl,pins = <
 201                         VF610_PAD_PTD0__QSPI0_A_QSCK    0x397f
 202                         VF610_PAD_PTD1__QSPI0_A_CS0     0x397f
 203                         VF610_PAD_PTD2__QSPI0_A_DATA3   0x397f
 204                         VF610_PAD_PTD3__QSPI0_A_DATA2   0x397f
 205                         VF610_PAD_PTD4__QSPI0_A_DATA1   0x397f
 206                         VF610_PAD_PTD5__QSPI0_A_DATA0   0x397f
 207                         VF610_PAD_PTD7__QSPI0_B_QSCK    0x397f
 208                         VF610_PAD_PTD8__QSPI0_B_CS0     0x397f
 209                         VF610_PAD_PTD11__QSPI0_B_DATA1  0x397f
 210                         VF610_PAD_PTD12__QSPI0_B_DATA0  0x397f
 211                 >;
 212         };
 213
 214         pinctrl_uart1: uart1grp {
 215                 fsl,pins = <
 216                         VF610_PAD_PTB4__UART1_TX                0x21a2
 217                         VF610_PAD_PTB5__UART1_RX                0x21a1
 218                 >;
 219         };
 220 };
 221
 222 &nfc {
 223         pinctrl-names = "default";
 224         pinctrl-0 = <&pinctrl_nfc>;
 225
 226         status = "okay";
 227 };
 228
 229 &uart1 {
 230         pinctrl-names = "default";
 231         pinctrl-0 = <&pinctrl_uart1>;
 232
 233         status = "okay";
 234 };
 235
 236 &qspi0 {
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&pinctrl_qspi0>;
 239
 240         bus-num = <0>;
 241         num-cs = <2>;
 242         status = "okay";
 243
 244         qflash0: spi_flash@0 {
 245                 #address-cells = <1>;
 246                 #size-cells = <1>;
 247                 compatible = "spi-flash";
 248                 spi-max-frequency = <108000000>;
 249                 reg = <0>;
 250         };
 251
 252         qflash1: spi_flash@1 {
 253                 #address-cells = <1>;
 254                 #size-cells = <1>;
 255                 compatible = "spi-flash";
 256                 spi-max-frequency = <66000000>;
 257                 reg = <1>;
 258         };
 259 };